Transistor-Transistor Logic and BiCMOS
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8-1Laboratory of Reliable Computing
Transistor-Transistor Logic and BiCMOS
Dr. T.Y. ChangNTHU EE
2007.12.11_13
8-2Laboratory of Reliable Computing
Introduction Diode-Transistor Logic Basic TTL NAND gate Schottky TTL BiCMOSText Book: D.A. Neamen, Electronic Circuits An
alysis And Design, 2nd ed. Chapters 17.
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Parameters
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Diode-Transistor Logic
Logic-1=5VLogic-0=0.1V
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Example 17.8 @p1137 Find Is and Vs in DTL as shown in Fig.
17.20 with =25.
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Evolution
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Multi-Emitter Cross Section
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TTL Inputs
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TTLEx 17.9 Find Is, Vs, and Max. Fanout of Fig. 17.24. R=0.1, =25.
• If No Rc CalledOpen-Collector TTL (OC TTL)• Wired-AND:Connects outputs of OC TTLsand adds an Rc
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TTL with Totem-Pole Output
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TTL Layout
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Fanout
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Modified Totem-Pole TTL
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Tristate Output
=0 switch open=1 switch on
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Schottky BJT
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Schottky TTL
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Low-Power Schottky TTL
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Example 17.12 @p1154 Calculate power dissipation in Fig. 17.34 with =25, V=0.7V, VCE(sat)=0.4V.
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Advanced Schottky TTL
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BiCMOS CMOS
Low Power Slower
BJT Faster High Power
Core: CMOS, Interface: BJT
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Basic BiCMOS Inverter Totem-Pole Configuration (Q1-Q2) Turn-off time VOH=VDD － VBE(ON) VOL=VBE(ON)
01
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BiCMOS Inverters
=VBE(ON)
or= VDD VBE(ON)
=0V or= VDD
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BiCMOS Inverter I Reduce Turn-off time “bleeder resistors” R1 and R2 are added VOH=VDD － VBE(ON) VOL=VBE(ON)
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BiCMOS Inverter II Reduce Turn-off time VOH=VDD and VOL=0
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BiCMOS NAND2 Gate
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BiCMOS NOR
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Problem (Not HW) Implement E=AB+CD in two-level TTL gates. Implement a BiCMOS NAND gate.
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Solutions E=AB+CD =((AB)’ (CD)’)’
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