1/19/2018 1 Digital Logic and Design (Course Code: EE222) Lecture 6: Logic Families Indian Institute of Technology Jodhpur, Year 2017‐2018 Course Instructor: Shree Prakash Tiwari Email: [email protected]b h //h / / Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ 1 Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only Overview • Early families (DL, RTL) • TTL • Evolution of TTL family • CMOS family and its evolution 2
13
Embed
Digital Logic and Design - home.iitj.ac.inhome.iitj.ac.in/~sptiwari/DLD/Lecture6_DLD.pdf · Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
1/19/2018
1
Digital Logic and Design (Course Code: EE222)
Lecture 6: Logic Families
Indian Institute of Technology Jodhpur, Year 2017‐2018
b h //h / /Webpage: http://home.iitj.ac.in/~sptiwari/
Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/
1
Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only
Overview
• Early families (DL, RTL)
• TTL
• Evolution of TTL family
• CMOS family and its evolution
2
1/19/2018
2
Logic families
Diode Logic (DL)• simplest; does not scale• NOT not possible (need =• NOT not possible (need an active element)
• replace diode switch with a transistor switch• can be cascaded• large power draw
3
Logic families
Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification• reduced power consumption
=
reduced power consumption• faster than RTL
DL AND gate Saturating inverter
4
1/19/2018
3
VOH(min) – The minimum voltage level at an output in the logical “1” state under defined load conditions
VOL(max) – The maximum voltage level at an output in the logical
Logic families: V levels
“0” state under defined load conditions
VIH(min) – The minimum voltage required at an input to be recognized as “1” logical state
VIL(max) – The maximum voltage required at an input that still will be recognized as “0” logical state
VOH VIH VOL VIL
5
IOH – Current flowing into an output in the logical “1” state under specified load conditions
IOL – Current flowing into an output in the logical “0” state under
Logic families: I requirements
OL g p gspecified load conditions
IIH – Current flowing into an input when a specified HI level is applied to that input
IIL – Current flowing into an input when a specified LO level is applied to that input
VOH VIH VOL VIL
IOH IIH IOL IIL
6
1/19/2018
4
Fanout: the maximum number of logic inputs (of the same logic family) that an output can drive reliably
Logic families: fanout
DC fanout = min( )IL
OL
IH
OH
I
I
I
I,
7
Logic families: propagation delay
TPD,HL TPD,LH
TPD,HL – input‐to‐output propagation delay from HI to LO output
TPD,LH – input‐to‐output propagation delay from LO to HI output
Speed-power product: TPD Pavg
8
1/19/2018
5
Logic families: noise margin
HI state noise margin:VNH = VOH(min) – VIH(min)
VNH
LO state noise margin:VNL = VIL(max) – VOL(max)
Noise margin:
VNL
gVN = min(VNH,VNL)
9
CMOS Logic Gates
Inverter
2-input AND
10
2-input OR
2-input NAND2-input NOR
1/19/2018
6
CMOS Logic Gates
# f i t AND / OR NAND / NOR
Number of transistors per logic gate:
Thus in terms of transistor count it is “cheaper” to
# of inputs AND / OR NAND / NOR
2 6 4
3 8 6
4 10 8
5 12 10
Thus, in terms of transistor count, it is cheaper to design logic circuits using NAND and NOR gates.
11
Logic Families
• CMOS logic levels and noise immunity
1/19/2018
7
Logic Families
• The bipolar transistor as a logical switch
Logic Families
• Timing considerations
– all gates have a certain propagation delay time, tPDPD
– this is the average of the two switching times
)t(tt PLHPHLPD 21
1/19/2018
8
TTL
Bipolar Transistor-Transistor Logic (TTL) • First introduced by in 1964 (Texas Instruments)• TTL has shaped digital technology in many ways• Standard TTL family (e.g. 7400) is obsolete• Newer TTL families used (e.g. 74ALS00)
15
TTL
Bipolar Transistor-Transistor Logic (TTL)
Distinct features• Multi emitter transistors• Multi‐emitter transistors
16
1/19/2018
9
TTL
A Standard TTL NAND gate
17
TTL
A standard TTL NAND gate with open collector output
18
1/19/2018
10
TTL evolution
Schottky series (74LS00) TTL• A major slowdown factor in BJTs is due to transistors going in/out of saturationgoing in/out of saturation• Shottky diode has a lower forward bias (0.25V)• When BC junction would become forward biased, the Schottky diode bypasses the current preventing the transistor from going into saturation
19
TTL family evolution
Legacy: don’t use in new designs
Widely used today
20
1/19/2018
11
ECL
Emitter-Coupled Logic (ECL)• PROS: Fastest logic family available (~1ns)• CONS: low noise margin and high power dissipationCONS: low noise margin and high power dissipation• Operated in emitter coupled geometry (recall differential amplifier or emitter‐follower), transistors are biased and operate near their Q‐point (never near saturation!)• Logic levels. “0”: –1.7V. “1”: –0.8V• Such strange logic levels require extra effort when interfacing to TTL/CMOS logic families.
21
CMOS
Complimentary MOS (CMOS)• Other variants: NMOS, PMOS (obsolete)• Very low static power consumptionVery low static power consumption• Scaling capabilities (large integration all MOS)• Full swing: rail‐to‐rail output• Things to watch out for:
– don’t leave inputs floating (in TTL these will float to HI, in CMOS you get undefined behaviour)– susceptible to electrostatic damage (finger of death)
22
1/19/2018
12
CMOS/TTL power requirements
• TTL power essentially constant (no frequency dependence)• CMOS power scales as f C V2CMOS power scales as f C V
• At high frequencies (>> MHz) CMOS dissipates more power than TTL
frequency supply volt.
eff. capacitance
• Overall advantage is still for CMOS even for very fast chips – only a relatively small portion of complicated circuitry operates at highest frequencies
23
CMOS family evolutionobsolete
• Reduction of dynamic losses through General trend:
y gsuccessively decreasing supply voltages: 12V 5V 3.3V 2.5V 1.8VCD4000 LVC/ALVC/AVC• Power reduction is one of the keys to progressive growth of integration