Fundamentals of Computer Systems - Columbia Universitysedwards/classes/2016/3827-summer/seque… · Summer 2016. State-Holding Elements Bistable Elements RS Latch D Latch Positive-Edge-Triggered
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Fundamentals of Computer SystemsSequential Logic
Stephen A. Edwards
Columbia University
Summer 2016
State-Holding ElementsBistable ElementsRS LatchD LatchPositive-Edge-Triggered D Flip-FlopD Flip-Flop with Enable
Synchronous Digital LogicThe Synchronous ParadigmShift RegistersCounters
Timing in Synchronous CircuitsFlip-Flop TimingTiming in Synchronous CircuitsClock Skew
State-Holding Elements
Bistable Elements
Q Q
Q
Q
Equivalent circuits; right is more traditional.
Two stable states:
0
1
1
0
A Bistable in the Wild
This “debounces” the coin switch.
Breakout, Atari 1976.
RS Latch
R
S
Q
Q
Q
Q
S
R
R S Q Q
0 0
Q
0 11 01 1
RS Latch
0R
1S
1Q
0 Q
Q
Q
S
R
R S Q Q
0 0
Q
0 1 1 0 Set1 01 1
R
S
Q
QSet
RS Latch
0R
0S
1Q
0 Q
Q
Q
S
R
R S Q Q
0 0 Q Q Hold0 1 1 0 Set1 01 1
R
S
Q
QHold, State 1
RS Latch
1R
0S
0Q
1 Q
Q
Q
S
R
R S Q Q
0 0 Q Q Hold0 1 1 0 Set1 0 0 1 Reset1 1
R
S
Q
QReset
RS Latch
0R
0S
0Q
1 Q
Q
Q
S
R
R S Q Q
0 0 Q Q Hold0 1 1 0 Set1 0 0 1 Reset1 1
R
S
Q
QHold, State 0
RS Latch
1R
1S
0Q
0 Q
Q
Q
S
R
R S Q Q
0 0 Q Q Hold0 1 1 0 Set1 0 0 1 Reset1 1 0 0 Bad
R
S
Q
QHuh?
RS Latch
0R
1S
1Q
0 Q
Q
Q
S
R
R S Q Q
0 0 Q Q Hold0 1 1 0 Set1 0 0 1 Reset1 1 0 0 Bad
R
S
Q
QSet
RS Latch
0R
0S
1Q
0 Q
Q
Q
S
R
R S Q Q
0 0 Q Q Hold0 1 1 0 Set1 0 0 1 Reset1 1 0 0 Bad
R
S
Q
QHold, State 1
RS Latch
1R
1S
0Q
0 Q
Q
Q
S
R
R S Q Q
0 0 Q Q Hold0 1 1 0 Set1 0 0 1 Reset1 1 0 0 Bad
R
S
Q
QHuh?
RS Latch
0R
0S
XQ
X Q
Q
Q
S
R
R S Q Q
0 0 Q Q Hold0 1 1 0 Set1 0 0 1 Reset1 1 0 0 Bad
R
S
Q
QUndefined
SR Latches in the Wild
Generates horizontal and vertical synchronizationwaveforms from counter bits.Stunt Cycle, Atari 1976.
D Latch
Q
Q
D
CQ
Q
D
C
inputs outputs
C D Q Q
0 X Q Q1 0 0 11 1 1 0
A Challenge
A simple traffic light controller.
Want the lights to cycle green-yellow-red.
D
C
Q
D
C
Q
D
C
Q
R
Y
G
Does this work?
Positive-Edge-Triggered D Flip-Flop
Master Slave
D
C
Q D
C
Q
C
D
CM CS
D′Q D Q
1 0
C
D
CMD′
CSQ
transparent
opaque
Positive-Edge-Triggered D Flip-Flop
Master Slave
D
C
Q D
C
Q
C
D
CM CS
D′Q D Q
1 0
C
D
CMD′
CSQ
transparent
opaque
Positive-Edge-Triggered D Flip-Flop
Master Slave
D
C
Q D
C
Q
C
D
CM CS
D′Q D Q
0 1
C
D
CMD′
CSQ
transparent
opaque
opaque
transparent
Positive-Edge-Triggered D Flip-Flop
Master Slave
D
C
Q D
C
Q
C
D
CM CS
D′Q D Q
0 1
C
D
CMD′
CSQ
transparent
opaque
opaque
transparent
Positive-Edge-Triggered D Flip-Flop
Master Slave
D
C
Q D
C
Q
C
D
CM CS
D′Q D Q
1 0
C
D
CMD′
CSQ
transparent
opaque
opaque
transparent
transparent
opaque
Positive-Edge-Triggered D Flip-Flop
Master Slave
D
C
Q D
C
Q
C
D
CM CS
D′Q D Q
0 1
C
D
CMD′
CSQ
transparent
opaque
opaque
transparent
transparent
opaque
opaque
transparent
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.
D Q
D Q
D Q
CLK
R
Y
G
CLK
R
Y
G
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.
D Q
D Q
D Q
CLK
R
Y
G
CLK
R
Y
G
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.
D Q
D Q
D Q
CLK
R
Y
G
CLK
R
Y
G
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.
D Q
D Q
D Q
CLK
R
Y
G
CLK
R
Y
G
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.
D Q
D Q
D Q
CLK
R
Y
G
CLK
R
Y
G
The Traffic Light Controller with Reset
D Q
D Q
D Q
CLK
RESET
R
Y
G
CLK
RESET
R
Y
G
The Traffic Light Controller with Reset
D Q
D Q
D Q
CLK
RESET
R
Y
G
CLK
RESET
R
Y
G
The Traffic Light Controller with Reset
D Q
D Q
D Q
CLK
RESET
R
Y
G
CLK
RESET
R
Y
G
The Traffic Light Controller with Reset
D Q
D Q
D Q
CLK
RESET
R
Y
G
CLK
RESET
R
Y
G
The Traffic Light Controller with Reset
D Q
D Q
D Q
CLK
RESET
R
Y
G
CLK
RESET
R
Y
G
The Traffic Light Controller with Reset
D Q
D Q
D Q
CLK
RESET
R
Y
G
CLK
RESET
R
Y
G
D Flip-Flop with Enable
D Q Q01D
C
E
C E D Q
↑ 0 X Q↑ 1 0 0↑ 1 1 10 X X Q1 X X Q
D QE
C
DQ
What’s wrong with thissolution?
Asynchronous Preset/Clear
D QPRE
CLR
CLK
D
PRE
CLR
Q
The Traffic Light Controller w/ Async. Reset
D QPRE
CLR
D QPRE
CLR
D QPRE
CLR
CLKR
Y
G
RESET
The Synchronous Digital Logic Paradigm
Gates and Dflip-flops only
Each flip-flopdriven by thesame clock
Every cyclicpath containsat least oneflip-flop
CLSTATE
NEXT STATE
INPUTS OUTPUTS
CLOCK
Cool Sequential Circuits: Shift Registers
A
Q0 Q1 Q2
Q3
CLK
A Q0Q1Q2Q3
0 X X X X1 0 X X X1 1 0 X X0 1 1 0 X1 0 1 1 00 1 0 1 10 0 1 0 10 0 0 1 01 0 0 0 10 1 0 0 0
Universal Shift Register
S1S0
0123
D0Q0
0123
D1Q1
0123
D2Q2
0123
D3Q3
CLK
R
L
S1 S0 Q3 Q2 Q1 Q0
0 0 R Q3 Q2 Q10 1 D3 D2 D1 D01 0 Q3 Q2 Q1 Q01 1 Q2 Q1 Q0 L
S1 S0 Operation
0 0 Shift right0 1 Load1 0 Hold1 1 Shift left
Cool Sequential Circuits: Counters
Cycle through sequences of numbers, e.g.,
00 01 10 11
The 74LS163 Synchronous Binary Counter
Flip-Flop Timing
CLK
D
Q
tsu
Setup Time: Time beforethe clock edge after whichthe data may not change
Flip-Flop Timing
CLK
D
Q
tsu th
Setup Time: Time beforethe clock edge after whichthe data may not change
Hold Time: Time after theclock edge after which thedata may change
Flip-Flop Timing
CLK
D
Q
tsu th
tp(min)
Setup Time: Time beforethe clock edge after whichthe data may not change
Hold Time: Time after theclock edge after which thedata may change
Minimum PropagationDelay: Time from clockedge to when Q mightstart changing
Flip-Flop Timing
CLK
D
Q
tsu th
tp(min)
tp(max)
Setup Time: Time beforethe clock edge after whichthe data may not change
Hold Time: Time after theclock edge after which thedata may change
Minimum PropagationDelay: Time from clockedge to when Q mightstart changing
Maximum PropagationDelay: Time from clockedge to when Qguaranteed stable
Timing in Synchronous Circuits
CL· · · · · ·Q D
CLK
CLK
Q
D
tc
tc: Clock period. E.g., 10 ns for a 100 MHz clock
Timing in Synchronous Circuits
CL· · · · · ·Q D
CLK
CLK
Q
D
tp(min,FF) tp(min,CL)
Sufficient Hold Time?
Hold time constraint: how soon after the clock edge can Dstart changing? Min. FF delay + min. logic delay
Timing in Synchronous Circuits
CL· · · · · ·Q D
CLK
CLK
Q
D
tp(max,FF)tp(max,CL)
Sufficient Setup Time?
Setup time constraint: when before the clock edge is Dguaranteed stable? Max. FF delay + max. logic delay
Clock Skew: What Really Happens
CL· · · · · ·Q DCLK1
CLK
CLK2
CLK1
CLK2
Q
Dtp(min,FF) tp(min,CL)
tskew
Sufficient Hold Time?
CLK2 arrives late: clock skew reduces hold time
Clock Skew: What Really Happens
CL· · · · · ·Q DCLK1
CLK
CLK2
CLK1
CLK2
Q
Dtp(max,FF) tp(max,CL)
tskew
Sufficient Setup Time?
CLK2 arrives early: clock skew reduces setup time
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