TK2633TK2633
Introduction to Parallel Data Interfacing
Introduction to Parallel Data Interfacing
DR MASRI AYOB
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MPU interface to external devices through both parallel and serial interfaces.
Parallel data occur in system that use:
Displays
Keyboard
Printers (old printer)
Etc.
Serial data occurs in:
Some printers
Data communications
IntroductionIntroduction
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8255 can be programmed for data transfer in multipurpose mode, either as i/o or interrupt.
It has 24 I/O pins, that can be divided into two groups of 8-bit parallel ports: Port A and Port B, and the rest belong to Port C.
Port C can be used as an individual bit or group of 4-bit:CUPPER (CU)
CLOWER (CL)
Figure 1 shows 3 kind of port groups in 8255.
8255 PIA (Peripheral Interface Adapter)
8255 PIA (Peripheral Interface Adapter)
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8255A Programmable Peripheral Interface8255A Programmable Peripheral Interface
Figure 1. The pinout of the 8255 (PIA)
D0D1D2D3D4D5D6D7
RD
WR
A0A1
RESET
CS
PA0PA1PA2PA3PA4PA5PA6PA7
PB0PB1PB2PB3PB4PB5PB6PB7
PC0PC1PC2PC3PC4PC5PC6PC7
8255
PORT A
PORT B
PORT C
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8255A block diagram:Figure 2, shows two 8-bit ports (A and B), two 4-bit ports (CU dan CL), data bus buffer and control logic.
Figure 3 shows the table and pin configuration of 8255 and the equivalent circuit as control logic and input/output port.
8255A Programmable Peripheral Interface
8255A Programmable Peripheral Interface
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Figure 2:
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Figure 3:
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Control Logic.RD (Read): This control signal is to enable read operation. When the signal is low activated, the MPU will read the data from certain I/O ports.
WR (Write): This signal enable the write operation. When this signal is at logic low, the MPU will write to I/O ports or control registers.
RESET (Reset): An active high signal. Use to clear the control register and sets all ports to input mode. Is connected to the RESET OUT pin of MPU.
CS, A0 and A1: Signals to select device. CS is connected to a decoded address, whereas A0 and A1 are connected to MPU address.
8255 PIA8255 PIA
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8255 PIA8255 PIA
Control Logic.CS signal is a Master Chip Select, whereas A0 and A1 determine the input/output ports or control registers as tabulated in Table 1.
CS A1 A0Selection
0 0 0 port A
0 0 1 port B
0 1 0 port C
0 1 1 Control Register
1 X X 8255 is disabled
Table 1: The function of CS, A0 and A1
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8255A PIA: Example8255A PIA: Example
Figure 4
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Example:
The port address as shown in Figure 4 is determined by CS, A0 and A1 pins.
CS is active low when A7 = 1 and A6 to A2 are at logic 0.
When the signal is combined with A0 and A1, the port address is 80H to 83H as shown in Figure 5.
8255 PIA8255 PIA
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8255 PIA8255 PIA
Example:
Figure 5
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Control Word:Figure 6 shows the function of control register, the content in this register is known as Control Word which determines input/output ports.
This register is used to write control word when A0 and A1 are at logic 1.
Bit D7 in control register determines the I/O function or Set/Reset. If bit D7 = 1, bits D6- D0 determine the function of I/O in multiple modes as shown in Figure 6.
Suppose bit D7 = 0,
• the port C operates in Bit Set/Reset (BSR) mode. • The BSR control word doest not cause any effect to port
A and port B. • The port C command register sets (1) or resets (0) the
port C pins during mode 1 or mode 2 operation.
8255 PIA8255 PIA
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Three main concept to communicate to 8255:• Determine the port address of A, B and C using
CS, A1 and A0.
• Write control word in control register.• Write I/O instructions to communicate with
ports.
8255 PIA8255 PIA
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Functions of Control Word.
Figure 6:
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Figure 8 shows the function of 8255, categorized in two mode:
Set/Reset Bit (BSR) modeI/O mode.
The BSR mode is used to set or reset bit at port C.Whereas the I/O is divided into 3 groups:
Mode 0, Mode 1 and Mode 2.
Mode 0, all ports function as input or output (I/O function).Mode 1, is handshake mod, where port A and/or port B used port C as handshake bit.Mode 2, port A can be used as bi-directional data transfer port with port C as handshake port and port B will be in mode 1 or mode 2.
8255 Programmable Peripheral Interface8255 Programmable Peripheral Interface
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8255 PIA8255 PIA
Figure 8
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Mode 0: Input / Output ModeIn this mode port A and B use 8-bit I/O data and port C uses two ports 4-bit data.
The characteristics of mode 0 are:• Output is latched.• Input does not latched.• Ports do not have the capability of handshake
mode or interrupt mode.
8255A Programmable Peripheral Interface
8255A Programmable Peripheral Interface
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Mode 0: Input / Output ModeExample :
• Determine the port address of circuit in Figure 9.
• Determine the control word in Mode 0, in order to determine ports A and CU as output port and ports B and CL as input ports.
• Write a program to read DIP switch and display the reading from port B to port A, from port CL to port CU.
8255 PIA : Mode 08255 PIA : Mode 0
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Example :
Figure 9:
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8255 PIA: Example8255 PIA: Example
Solutions:
Port Address :• It is actually an I/O memory map.
• When A15 is active high, Chip Select signal is activated.
• Assuming all don’t care signals are at logic 0, therefore ports’ address are as follows:
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8255A Programmable Peripheral Interface8255A Programmable Peripheral Interface
Solution:Control Word:
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8255 PIA8255 PIA
Solution: ???
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BSR (Bit Set/Reset) mode.
The BSR mode will only affect to port C.
Set/Reset can be determined by entering certain control word to control register.
No change to the previous data when D7 change from 1 to 0; therefore the I/O ports A and B unchanged.
In BSR mode, the individual bit also can be used as ‘on / off’ switch.
8255 PIA8255 PIA
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8255A Programmable Peripheral Interface8255A Programmable Peripheral Interface
BSR Control Word.The written control word in control register, set/reset will take only one bit at a time, as follows:
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8255 PIA: BSR Mode8255 PIA: BSR ModeExample:
Write a BSR control word subroutine to set bit PC7 and PC3, and reset after 10ms. Use the schematic diagram as shown below.
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8255A Programmable Peripheral Interface8255A Programmable Peripheral Interface
Solution:BSR Control Word:
Port Address:
• As shown in previous example : 83H
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8255A Programmable Peripheral Interface8255A Programmable Peripheral Interface
Solution:Subroutine: Assuming that the delay subroutine has been determined earlier.
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Thank youQ&A