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Room: E-3-31 Phone: 03-8921 6726 [email protected] Dr Masri Ayob Dr Masri Ayob TK 2123 TK 2123 COMPUTER ORGANISATION & COMPUTER ORGANISATION & ARCHITECTURE ARCHITECTURE Lecture 5: CPU and Memory Lecture 5: CPU and Memory
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Room: E-3-31 Phone: 03-8921 6726 [email protected] Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Dec 19, 2015

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Page 1: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Room: E-3-31

Phone: 03-8921 6726

[email protected]

Dr Masri AyobDr Masri Ayob

TK 2123TK 2123COMPUTER ORGANISATION & COMPUTER ORGANISATION &

ARCHITECTUREARCHITECTURE

Lecture 5: CPU and MemoryLecture 5: CPU and Memory

Page 2: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK212322

ContentsContents

This lecture will discuss:This lecture will discuss:Computer Systems Organisation.Computer Systems Organisation. Instruction Execution.Instruction Execution.Design Principles for Modern Computers.Design Principles for Modern Computers.

Page 3: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK212333

Program ConceptProgram Concept

Hardwired systems are inflexibleHardwired systems are inflexibleGeneral purpose hardware can do General purpose hardware can do

different tasks, given correct control different tasks, given correct control signalssignals

Instead of re-wiring, supply a new set of Instead of re-wiring, supply a new set of control signalscontrol signals

Page 4: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK212344

What is a program?What is a program?

A sequence of stepsA sequence of stepsFor each step, an arithmetic or logical For each step, an arithmetic or logical

operation is doneoperation is doneFor each operation, a different set of For each operation, a different set of

control signals is neededcontrol signals is needed

Page 5: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK212355

Function of Control UnitFunction of Control Unit

For each operation a unique code is For each operation a unique code is providedprovidede.g. ADD, MOVEe.g. ADD, MOVE

A hardware segment accepts the code A hardware segment accepts the code and issues the control signalsand issues the control signals

We have a computer!We have a computer!

Page 6: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK212366

Components of ComputerComponents of Computer

Central Processing Unit (CPU) has:Central Processing Unit (CPU) has:The Control Unit (CU) The Control Unit (CU) the Arithmetic and Logic Unit (ALU).the Arithmetic and Logic Unit (ALU).

Data and instructions need to get into the Data and instructions need to get into the system and results outsystem and results out Input/outputInput/output

Temporary storage of code, data and Temporary storage of code, data and results is neededresults is neededMain memoryMain memory

Page 7: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK212377

Central Processing UnitCentral Processing Unit

The organisation of a simple computer with The organisation of a simple computer with one CPU and two I/O devicesone CPU and two I/O devices

Page 8: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK212388

CPU OrganizationCPU Organization

The data path of a typical Von Neumann machine.The data path of a typical Von Neumann machine.

Page 9: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK212399

Components of the CPUComponents of the CPU

The arithmetic/logic unit is the component of the The arithmetic/logic unit is the component of the CPU where data is held temporarily and where CPU where data is held temporarily and where calculations take place. calculations take place.

The control unit controls and interprets the The control unit controls and interprets the execution of instructions .execution of instructions .

The control unit determines the particular The control unit determines the particular instruction to be executed by reading the instruction to be executed by reading the contents of a program counter (PC), sometimes contents of a program counter (PC), sometimes called an instruction pointer, which is a part of called an instruction pointer, which is a part of the control unit. the control unit.

Page 10: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231010

Components of the CPUComponents of the CPU

Normally, instructions are executed Normally, instructions are executed sequentially. sequentially. The sequence of instructions is modified by The sequence of instructions is modified by

executing instructions that change the executing instructions that change the contents of the program counter.contents of the program counter.

A Memory Management Unit within the A Memory Management Unit within the control unit supervises the fetching of control unit supervises the fetching of instructions and data from memory. instructions and data from memory.

Page 11: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231111

The Concept Of Registers The Concept Of Registers

A register is a single, permanent storage location within A register is a single, permanent storage location within the CPU used for a particular, defined purpose. the CPU used for a particular, defined purpose.

A register is used to hold a binary value temporarily for A register is used to hold a binary value temporarily for storage, for manipulation, and/or for simple calculations.storage, for manipulation, and/or for simple calculations.

Each register is wired within the CPU to perform its Each register is wired within the CPU to perform its specific role. specific role. each register serves a particular purpose. each register serves a particular purpose. The register’s size, the way it is wired, and even the The register’s size, the way it is wired, and even the

operations that take place in the register reflect the operations that take place in the register reflect the specific function that the register performs in the specific function that the register performs in the computer. computer.

Page 12: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231212

The Concept Of Registers The Concept Of Registers

They are not addressed as a memory location, but instead They are not addressed as a memory location, but instead are manipulated directly by the control unit during the are manipulated directly by the control unit during the execution of instructions. execution of instructions.

They may be as small as a single bit or as wide as several They may be as small as a single bit or as wide as several bytes, ranging usually from one to 128 bits. bytes, ranging usually from one to 128 bits.

A register may hold:A register may hold: data being processed, data being processed, an instruction being executed, an instruction being executed, a memory or I/O address to be accessed, a memory or I/O address to be accessed, or even special binary codes used for some other purpose.or even special binary codes used for some other purpose.

Some registers serve many different purposes, while others Some registers serve many different purposes, while others are designed to perform a single, specialised task. are designed to perform a single, specialised task.

Page 13: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231313

The Concept Of Registers The Concept Of Registers

Registers are basic working components of the CPU.Registers are basic working components of the CPU. The control unit contains several important registers:The control unit contains several important registers:

the program counter (PC) register holds the address of the current the program counter (PC) register holds the address of the current instruction being executed.instruction being executed.

The instruction register (IR) holds the actual instruction being The instruction register (IR) holds the actual instruction being executed currently by the computer. executed currently by the computer.

The memory address register (MAR) holds the address of a The memory address register (MAR) holds the address of a memory location.memory location.

The memory data register (MDR), sometimes known as the memory The memory data register (MDR), sometimes known as the memory buffer register, will hold a data value that is being stored to or buffer register, will hold a data value that is being stored to or retrieved from the memory location currently addressed by the retrieved from the memory location currently addressed by the memory address register. memory address register.

Page 14: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231414

The Concept Of Registers The Concept Of Registers

The CU also contain several 1-bit registers, The CU also contain several 1-bit registers, sometimes known as flags, that are used to sometimes known as flags, that are used to allow the computer to keep track of special allow the computer to keep track of special conditions such as:conditions such as:arithmetic carry and overflow,arithmetic carry and overflow,power failure, and internal computer error. power failure, and internal computer error.

Usually, several flags are grouped into one Usually, several flags are grouped into one or more status registers.or more status registers.

Page 15: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231515

The Concept Of Registers The Concept Of Registers

Most registers support four primary types of Most registers support four primary types of operations:operations: Registers can be loaded with values from other locations, in Registers can be loaded with values from other locations, in

particular from other registers or from memory locations. particular from other registers or from memory locations. Data from another location can be added to or subtracted Data from another location can be added to or subtracted

from the value previously stored in a register, leaving the from the value previously stored in a register, leaving the sum or difference in the register.sum or difference in the register.

Data in a register can be shifted or rotated right or left by Data in a register can be shifted or rotated right or left by one or more bits.one or more bits.

The value of data in a register can be tested for certain The value of data in a register can be tested for certain conditions, such as zero, positive, negative, or too large to conditions, such as zero, positive, negative, or too large to fit in the register.fit in the register.

Page 16: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231616

THE MEMORY UNITTHE MEMORY UNIT

The memory address register (MAR) and the memory data The memory address register (MAR) and the memory data register (MDR), act is an interface between the CPU and register (MDR), act is an interface between the CPU and memory. memory. The MDR is called the memory buffer register by some The MDR is called the memory buffer register by some

computer manufacturers.computer manufacturers. Each cell in the memory unit holds one bit of data. Each cell in the memory unit holds one bit of data. The cells are organized in rows. The cells are organized in rows.

Each row consists of a group of one or more bytes. Each row consists of a group of one or more bytes. In modern computers, it is common to address eight bytes In modern computers, it is common to address eight bytes

at a time to speed up memory access between the CPU at a time to speed up memory access between the CPU and memory. and memory.

Page 17: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231717

Page 18: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231818

THE MEMORY UNITTHE MEMORY UNIT

The MAR holds the address in the memory that is to be The MAR holds the address in the memory that is to be “opened” for data. “opened” for data. The MAR is connected to a decoder that interprets the address and The MAR is connected to a decoder that interprets the address and

activates a single address line into the memory. activates a single address line into the memory.

The MDR is designed such that it is effectively connected to The MDR is designed such that it is effectively connected to every cell in the memory unit. every cell in the memory unit. Each bit of the MDR is connected in a column to the corresponding Each bit of the MDR is connected in a column to the corresponding

bit of every location in memory. bit of every location in memory. The addressing method assures that only a single row of cells is The addressing method assures that only a single row of cells is

activated at any given time. activated at any given time. Only one memory location is addressed at any one time. Only one memory location is addressed at any one time.

Page 19: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21231919

Page 20: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21232020

Memory Capacity Memory Capacity

The number of bits in the MAR determines The number of bits in the MAR determines how many different address locations can be how many different address locations can be decoded.decoded.For a MAR of width k bits, the number of For a MAR of width k bits, the number of

possible memory addresses ispossible memory addresses is

M = 2M = 2kk

For example: A 32-bit memory address allows a For example: A 32-bit memory address allows a memory capacity of 4 gigabytes (GB) memory capacity of 4 gigabytes (GB)

Page 21: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21232121

Memory Capacity Memory Capacity

The size of the word to be retrieved or stored in The size of the word to be retrieved or stored in a single operation is determined by the size of a single operation is determined by the size of the MDR and by the width of the bus connecting the MDR and by the width of the bus connecting memory to the CPU. memory to the CPU. In most modern computers, data and instructions In most modern computers, data and instructions

found in memory are addressed in multiples of 8-bit found in memory are addressed in multiples of 8-bit bytes. bytes.

the MDR is usually designed to retrieve the data or the MDR is usually designed to retrieve the data or instruction(s) from a sequence of several successive instruction(s) from a sequence of several successive addresses all at once, and the MDR will be several addresses all at once, and the MDR will be several bytes wide. bytes wide.

Page 22: Room: E-3-31 Phone: 03-8921 6726 masri@ftsm.ukm.my Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory.

Prepared by: Dr Masri AyobPrepared by: Dr Masri Ayob - TK2123 - TK21232222

Thank youThank youQ & AQ & A