S emb t4-arch_cpu

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Maths is not everything

Embedded Systems4 - Hardware Architecture

CPUCPUInput/Output mechanisms

MemoryBuses And Aux

Input/Output interfacesPower Management

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CPUISA - Introduction

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Instruction Set Architecture

The computer ISA defines all of the programmer-visible components and operations of the computer

Memory organizationaddress space -- how may locations can be addressed?addressibility -- how many bits per location?

Register sethow many? what size? how are they used?

Instruction setopcodesdata typesaddressing modes

ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).

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von Neumann architecture

Memory holds data & instructions.

Central processing unit (CPU) fetches instructions from memory.

Separate CPU and memory distinguishes programmable computer.

CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc.

CPU

PC200

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CPU + memory

memory

address

IR

data

ADD r5,r1,r3200 ADD r5,r1,r3

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Harvard architecture

CPU

PCdata memory

program memory

address

data

address

data

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von Neumann vs. Harvard

Harvard can’t use self-modifying code.

Harvard allows two simultaneous memory fetches.

Most DSPs use Harvard architecture for streaming data:

greater memory bandwidth;

more predictable bandwidth.

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RISC vs. CISC

Complex instruction set computer (CISC):

many addressing modes;

many operations.

Reduced instruction set computer (RISC):

load/store;

pipelinable instructions.

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Instruction set characteristics

Fixed vs. variable length.Addressing modes.Number of operands.Types of operands.

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Multiple implementations

Successful architectures have several implementations:

varying clock speeds;

different bus widths;

different cache sizes;

...

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Assembly language

Basic features:

One instruction per line.

Labels provide names for addresses (usually in first column).

Instructions often start in later columns.

Columns run to end of line.

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ARM assembly language example

header

LDR r1,[r4]SUB r0,r0,r1 ; 3 addresses instruction

MOV sp,#INIT_SP ; set-up stack pointer ADR lr, start+1 ; Processor starts in ARM state, BX lr ; so small ARM code header used ; to call Thumb main program.

CODE16 ; Subsequent instructions are Thumb.start

;**********************************************************************;* This an example of 16 bits code (Thumb mode);**********************************************************************

BL irq_init ; init. interruptsforever BL seg_rot ; check display of hex digits MOV r0,#0xf BL leds_on ; sw on the ledschksw0 BL sw_rd ; read DIP_SW port, r0 carries word AND r0,r0 ; check if any DIP_SW has been mod. BEQ chksw0 ; if not, keep checking

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MSP430 assembly language example

MOV.w #0x05,R5!! ; move source to destination ! ! ! ; assign a hexadecimal value 0x05 to Register R5

MOV.w #0x03,R6!! ; move source to destination ! ! ! ; assign a hexadecimal value 0x03 to Register R6

CMP.w! R6, R5! ! ; compare source to destination! ! ! ; R5-R6 = 5-3 = 2 greater than 0, so R5 > R6

JNE! somewhere! ; jump if not equal! ! ; The program will jump to “somewhere” because R5 ≠ R6

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CPU ARM ISA

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ARM versions

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ARM core family

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ARM Processor Core

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� Current low-end ARM core for applications like digital mobile phones

� TDMI

� T: Thumb, 16-bit instruction set

� D: on-chip Debug support, enabling the processor to halt in response to a debug request

� M: enhanced Multiplier, yield a full 64-bit result, high performance

� I: EmbeddedICE hardware

� Von Neumann architecture

� 3-stage pipeline

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ARM programming model

r0r1r2r3r4r5r6r7

r8r9r10r11r12r13r14

link reg. in BL

r15 (PC)

CPSR

31 0

N Z C V

Status Register

sp for procedure linkage

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ARM core structure

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Endianness

Relationship between bit and byte/word ordering defines endianness:

byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3

bit 31 bit 0 bit 31 bit 0

little-endian big-endian

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ARM data types

Word is 32 bits long.

Word can be divided into four 8-bit bytes.

ARM addresses can be 32 bits long.

Address refers to byte.

Address 4 starts at byte 4.

Can be configured at power-up as either little- or big-endian mode.

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ARM states

When the processor is executing in ARM state:All instructions are 32 bits wide

All instructions must be word aligned

When the processor is executing in Thumb state:All instructions are 16 bits wide

All instructions must be halfword aligned

When the processor is executing in Jazelle state:All instructions are 8 bits wide

Processor performs a word access to read 4 instructions at once

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Processor Core Vs CPU Core

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Processor CoreThe engine that fetches instructions and execute them

E.g.: ARM7TDMI, ARM9TDMI, ARM9E-S

CPU CoreConsists of the ARM processor core and some tightly coupled function blocksCache and memory management blocksE.g.: ARM710T, ARM720T, ARM74T, ARM920T, ARM922T, ARM940T, ARM946E-S, and ARM966E-S ARM710T

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ARM status bits

Every arithmetic, logical, or shifting operation sets CPSR bits:

N (negative), Z (zero), C (carry), V (overflow).

Examples:

-1 + 1 = 0: NZCV = 0110.

231-1+1 = -231: NZCV = 0101.

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ARM data instructions

Basic format:ADD r0,r1,r2

Computes r1+r2, stores in r0.

Immediate operand:ADD r0,r1,#2

Computes r1+2, stores in r0.

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ARM data instructions

ADD, ADC : add (w. carry)SUB, SBC : subtract (w. carry)RSB, RSC : reverse subtract (w. carry)MUL, MLA : multiply (and accumulate)

AND, ORR, EORBIC : bit clearLSL, LSR : logical shift left/rightASL, ASR : arithmetic shift left/rightROR : rotate rightRRX : rotate right extended with C

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Data operation varieties

Logical shift:fills with zeroes.

Arithmetic shift:fills with ones.

RRX performs 33-bit rotate, including C bit from CPSR above sign bit.

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ARM comparison instructions

CMP : compareCMN : negated compareTST : bit-wise testTEQ : bit-wise negated testThese instructions set only the NZCV bits of CPSR.

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ARM move instructions

MOV, MVN : move (negated)!! MOV r0, r1 ; sets r0 to r1

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ARM load/store instructions

LDR, LDRH, LDRB : load (half-word, byte)STR, STRH, STRB : store (half-word, byte)Addressing modes:

register indirect : LDR r0,[r1]

with second register : LDR r0,[r1,-r2]

with constant : LDR r0,[r1,#4]

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ARM ADR pseudo-op

Cannot refer to an address directly in an instruction.Generate value by performing arithmetic on PC.ADR pseudo-op generates instruction required to calculate address:

ADR r1,FOO

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Example: C assignments

x = (a + b) - c;

Assembler:! ADR r4,a! ! ; get address for a

! LDR r0,[r4]!; get value of a

! ADR r4,b! ! ; get address for b, reusing r4

! LDR r1,[r4]!; get value of b

! ADD r3,r0,r1!; compute a+b

! ADR r4,c! ! ; get address for c

! LDR r2[r4]! ; get value of c

SUB r3,r3,r2!; complete computation of x

! ADR r4,x! ! ; get address for x

! STR r3,[r4]!; store value of x

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Example: C assignment

y = a*(b+c);

Assembler:! ADR r4,b ; get address for b

! LDR r0,[r4] ; get value of b

! ADR r4,c ; get address for c

! LDR r1,[r4] ; get value of c

! ADD r2,r0,r1 ; compute partial result

! ADR r4,a ; get address for a

! LDR r0,[r4] ; get value of a

! MUL r2,r2,r0 ; compute final value for y

! ADR r4,y ; get address for y

! STR r2,[r4] ; store y

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Example: C assignment

z = (a << 2) | (b & 15);

Assembler:! ADR r4,a ; get address for a


! MOV r0,r0,LSL 2 ; perform shift

! ADR r4,b ; get address for b

! LDR r1,[r4] ; get value of b

! AND r1,r1,#15 ; perform AND

! ORR r1,r0,r1 ; perform OR

! ADR r4,z ; get address for z

! STR r1,[r4] ; store value for z

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Additional addressing modes

Base-plus-offset addressing:LDR r0,[r1,#16]

Loads from location r1+16Auto-indexing increments base register:

LDR r0,[r1,#16]!

Post-indexing fetches, then does offset:LDR r0,[r1],#16

Loads r0 from r1, then adds 16 to r1.

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ARM flow of control

All operations can be performed conditionally, testing CPSR:

EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE

Branch operation:B #100

Can be performed conditionally.

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Example: if statement

if (a < b) { x = 5; y = c + d; } else x = c - d;

Assembler:; compute and test condition

! ADR r4,a ; get address for a


! ADR r4,b ; get address for b

! LDR r1,[r4] ; get value for b

! CMP r0,r1 ; compare a < b

! BGE fblock ; if a >= b, branch to false block

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If statement, cont’d.

; true block

! MOV r0,#5 ; generate value for x

! ADR r4,x ; get address for x

! STR r0,[r4] ; store x

! ADR r4,c ; get address for c


! ADR r4,d ; get address for d

! LDR r1,[r4] ; get value of d

! ADD r0,r0,r1 ; compute y

! ADR r4,y ; get address for y

! STR r0,[r4] ; store y

! B after ; branch around false block

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If statement, cont’d.

; false block

fblock ADR r4,c ; get address for c


! ADR r4,d ; get address for d

! LDR r1,[r4] ; get value for d

! SUB r0,r0,r1 ; compute a-b

! ADR r4,x ; get address for x

! STR r0,[r4] ; store value of x

after ...

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Example: Conditional instruction implementation

; true block

! MOVLT r0,#5 ; generate value for x

! ADRLT r4,x ; get address for x

! STRLT r0,[r4] ; store x

! ADRLT r4,c ; get address for c

! LDRLT r0,[r4] ; get value of c

! ADRLT r4,d ; get address for d

! LDRLT r1,[r4] ; get value of d

! ADDLT r0,r0,r1 ; compute y

! ADRLT r4,y ; get address for y

! STRLT r0,[r4] ; store y

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Conditional instruction implementation, cont’d.

; false block

! ADRGE r4,c ; get address for c

! LDRGE r0,[r4] ; get value of c

! ADRGE r4,d ; get address for d

! LDRGE r1,[r4] ; get value for d

! SUBGE r0,r0,r1 ; compute a-b

! ADRGE r4,x ; get address for x

! STRGE r0,[r4] ; store value of x

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ARM subroutine linkage

Branch and link instruction:BL foo

Copies current PC to r14.To return from subroutine:

MOV r15,r14

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Nested subroutine calls

Nesting/recursion requires coding convention:

f1!! LDR r0,[r13] ; load arg into r0 from stack

! ! ; call f2()

! ! STR r14,[r13]! ; store f1’s return adrs

! ! STR r0,[r13]! ; store arg to f2 on stack

! ! BL f2 ; branch and link to f2

! ! ; return from f1()

! ! SUB r13,#4 ; pop f2’s arg off stack

! ! LDR r15,[r13]#-4 ; restore register and return

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CPU MSP430 ISA

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MSP430 ISA

RISC/CISC machine27 orthogonal instructions

8 jump instructions

7 single operand instructions

12 double operand instructions

7 addressing modes.

8/16-bit instruction addressing formats.

Memory architecture16 16-bit registers

16-bit Arithmetic Logic Unit (ALU).

16-bit address bus (64K address space)

16-bit data bus (8-bit addressability)

8/16-bit peripherals

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MSP 430 Micro-Architecture

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MSP430 Registers

R0 (PC) – Program CounterThis register always points to the next instruction to be fetched

Each instruction occupies an even number of bytes. Therefore, the least significant bit (LSB) of the PC register is always zero.

After fetch of an instruction, the PC register is incremented by 2, 4, or 6 to point to the next instruction.

R1 (SP) – Stack PointerThe MSP430 CPU stores the return address of routines or interrupts on the stack

User programs store local data on the stack

The SP can be incremented or decremented automatically with each stack access

The stack “grows down” thru RAM and thus SP must be initialized with a valid RAM address

SP always points to an even address, so its LSB is always zero

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MSP430 Registers

R2 (SR/CG1) – Status RegisterThe status of the MSP430 CPU is contained in register R2Only accessible through register addressing mode - all other addressing modes are reserved to support the constants generator

Carry bitCZero bitZ

Negative bitNGeneral interrupt enableGIE

Turns off the CPU.CPUOFFOscillator offOSCOFF

Turns off the DCO dc generator.SCG0Turns off the SMCLK.SCG1

Overflow bitV

R3 (CG2) – Constant Generator

R4-R15 – General Purpose registers

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16 bit Arithmetic Logic Unit (ALU).

Performs instruction arithmetic and logical operations

Instruction execution affects the state of the following flags:

Zero (Z)Carry (C)Overflow (V)Negative (N)

The MCLK (Master) clock signal drives the CPU.

MSP430 ALU

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MSP430 Memory Organization

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MSP430X CPU

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MSP430X Memory Organization

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MSP430X Registers

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MSP430 Instructions

There are three formats used to encode instructions for processing by the CPU core

Double operandSingle operandJumps

The instructions for double and single operands, depend on the suffix used, (.w) word or (.b) byteThese suffixes allow word or byte data accessIf the suffix is ignored, the instruction processes word data by default

1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

4 to 16 Decoder

Op-code Op-code Instruction Format 0000 Undefined Single Operand 0001 RCC, SWPB, RRA, SXT, PUSH, CALL, RETI 0010 JNE, JEQ, JNC, JC Jumps 0011 JN, JGE, JL, JMP 0100 MOV

Double Operand

0101 ADD 0110 ADDC 0111 SUBC 1000 SUB 1001 CMP 1010 DADD 1011 BIT 1100 BIC 1101 BIS 1110 XOR 1111 AND RMR©2012


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MSP430 Instructions

Memory 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 mov.w r5,r4 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 rrc.w r5 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 jc main 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 mov.w #0x0600,r1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

PC

Instruction Register15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

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MSP430X Instructions

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MPS430 Instruction Formats

Format I: Instructions with two operands:

Format II: Instruction with one operand:

Format III: Jump instructions:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code S-reg Ad b/w As D-reg

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code b/w Ad D/S-reg

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Op-code Condition 10-bit, 2’s complement PC offset

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Format I: Double Operand

Double operand instructions:Mnemonic Operation Description Arithmetic instructions ADD(.B or .W) src,dst src+dst→dst Add source to destination ADDC(.B or .W) src,dst src+dst+C→dst Add source and carry to destination DADD(.B or .W) src,dst src+dst+C→dst (dec) Decimal add source and carry to destination SUB(.B or .W) src,dst dst+.not.src+1→dst Subtract source from destination SUBC(.B or .W) src,dst dst+.not.src+C→dst Subtract source and not carry from destination Logical and register control instructions AND(.B or .W) src,dst src.and.dst→dst AND source with destination BIC(.B or .W) src,dst .not.src.and.dst→dst Clear bits in destination BIS(.B or .W) src,dst src.or.dst→dst Set bits in destination BIT(.B or .W) src,dst src.and.dst Test bits in destination XOR(.B or .W) src,dst src.xor.dst→dst XOR source with destination Data instructions CMP(.B or .W) src,dst dst-src Compare source to destination MOV(.B or .W) src,dst src→dst Move source to destination

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Example: Double Operand

Copy the contents of a register to another register

Assembly: mov.w r5,r4Instruction code: 0x4504

One word instruction

The instruction instructs the CPU to copy the 16-bit 2’s complement number in register r5 to register r4

Op-codemov

S-regr5

AdRegister

b/w16-bits

AsRegister

D-regr4

0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

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Format II: Single Operand

Single operand instructions:

Mnemonic Operation Description Logical and register control instructions RRA(.B or .W) dst MSB→MSB→…

LSB→C Roll destination right

RRC(.B or .W) dst C→MSB→…LSB→C Roll destination right through carry SWPB( or .W) dst Swap bytes Swap bytes in destination SXT dst bit 7→bit 8…bit 15 Sign extend destination PUSH(.B or .W) src SP-2→SP, src→@SP Push source on stack Program flow control instructions CALL(.B or .W) dst SP-2→SP,

PC+2→@SP dst→PC

Subroutine call to destination

RETI @SP+→SR, @SP+→SP Return from interrupt

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Example: Single Operand

Logically shift the contents of register r5 to the right through the status register carry

Assembly: rrc.w r5Instruction code: 0x1005


The CPU shifts the 16-bit register r5 one bit to the right (divide by 2) – the carry bit prior to the instruction becomes the MSB of the result while the LSB shifted out replaces the carry bit in the status register

Op-coderrc

b/w16-bits

AdRegister

D-regr5

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1

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Jump Instruction Format

Jump instructions are used to direct program flow to another part of the program.The condition on which a jump occurs depends on the Condition field consisting of 3 bits:

000: jump if not equal001: jump if equal010: jump if carry flag equal to zero011: jump if carry flag equal to one100: jump if negative (N = 1)101: jump if greater than or equal (N = V)110: jump if lower (N ≠ V)111: unconditional jump

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code Condition 10-bit, 2’s complement PC offset

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Jump Instruction Format

Jump instructions are executed based on the current PC and the status registerConditional jumps are controlled by the status bitsStatus bits are not changed by a jump instructionThe jump off-set is represented by the 10-bit, 2’s complement value:

Thus, the range of the jump is -511 to +512 words, (-1023 to 1024 bytes ) from the current instructionNote: Use a BR instruction to jump to any address

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Example: Jump Format

Continue execution at the label main if the carry bit is set

Assembly: jc mainInstruction code: 0x2fe4


The CPU will add to the incremented PC (R0) the value -28 x 2 if the carry is set

Op-codeJC

ConditionCarry Set

10-Bit, 2’s complement PC offset-28

0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0

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Source Addressing Modes

The MSP430 has four modes for the source address:

00 = Rs - Register 01 = x(Rs) - Indexed Register 10 = @Rs - Register Indirect 11 = @Rs+ - Indirect Auto-increment

In combination with registers R0-R3, three additional source addressing modes are available:

label - PC Relative, x(PC)&label – Absolute, x(SR)#n – Immediate, @PC+

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Destination Addressing Modes

There are two modes for the destination address:

0 = Rd - Register

1 = x(Rd) - Indexed Register

In combination with registers R0/R2, two additional destination addressing modes are available:

label - PC Relative, x(PC)

&label – Absolute, x(SR)

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00 = Register Mode

add.w r4,r10 ;r10 = r4 + r10

Registers

CPU Memory

ADDER

PC PC

R10

R4

IR Data Bus (1 cycle) 0x540a

0x540a

Address Bus

PC

ALU

Memory

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

0x0006 PC PC PC

R10

R4


0x541a

Address Bus

PC

ALU

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01 = Indexed Mode

add.w 6(r4),r10 ;r10 = M(r4+6) + r10

Memory

Registers

Address Bus

Data Bus (+1 cycle)

CPU

ADDER

PC PC

R10

R4


Address Bus

0x542a PC

ALU

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10 = Indirect Register Mode

add.w @r4,r10 ;r10 = M(r4) + r10

11 = Indirect Auto-increment Mode

Memory

Registers

Data Bus (+1 cycle)

CPU

ADDER

PC PC

R10

R4


Address Bus

PC 0x543a

Address Bus 0002

ALU

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add.w @r4+,r10 ;r10 = M(r4+) + r10

01 w/R0 = Symbolic Mode (PC Relative)

Memory

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

0x000c PC PC PC

PC

R10


Address Bus

0x501a PC

ALU

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add.w cte,r10 ;r10 = M(cte) + r10

01 w/R2 = Absolute Mode

Memory

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

0000 0xc018

PC PC PC

R10


Address Bus

0x521a PC

ALU

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add.w &cte,r10 ;r10 = M(cte) + r10

11 w/R0 = Immediate Mode

Memory

Registers

CPU

ADDER

PC PC PC

R10

Data Bus (+1 cycle)


Address Bus

PC 0x503a 0x0064

ALU

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add.w #100,r10 ;r10 = #100 + r10

Constant Generator

Memory

Registers

CPU

ADDER

PC PC

R10

0000 0001 0002 0004 0008 ffff


Address Bus

PC 0x531a

ALU

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add.w #1,r10 ;r10 = #1 + r10

3 Word Instruction (6 cycles)

Memory

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

0x000c PC PC PC

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

PC Data Bus (+1 cycle) 0x0218


Address Bus

0x501a PC PC

ALU

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add.w cte,var ;var = M(cte) + M(var)

Source Destination Example Rn x(Rn) Sym &abs @Rn @Rn+ #n Rn x(Rn) Sym &abs Len Operation mov r10,r11 • • 1 r10 → r11

mov 2(r5),6(r6) • • 3 M(2+r5) → M(6+r6)

mov EDE,TONI • • 3 M(EDE) → M(TONI)

mov &MEM,&TCDAT • • 3 M(MEM) → M(TCDAT)

mov @r10,r11 • • 1 M(r10) → r11

mov @r10+,tab(r6) • • 2 M(r10) → M(tab+r6) , r10+2 → r10

mov #45,TONI • • 3 #45 → M(TONI)

mov #2,&MEM C • 2 #2 → M(MEM)

mov #1,r11 C • 1 #1 → r11

mov #45,r11 • • 2 #45 → r11

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Addressing Mode Examples

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Cycles Per Instruction

Instruction timing:1 cycle to fetch instruction word

+1 cycle if source is @Rn, @Rn+, or #Imm

+2 cycles if source uses indexed mode1st to fetch base address2nd to fetch sourceIncludes absolute and symbolic modes

+2 cycles if destination uses indexed mode

+1 cycle if writing destination back to memory

+1 cycle if writing to PC (R0)

Jump instructions are always 2 cycles

Example Src Dst Cycles Length

add R5,R8 Rn Rm 1 1

add @R5,R6 @Rn Rm 2 1

mov @R5+,R0 @Rn+ PC 3 1

add R5,4(R6) Rn x(Rm) 4 2

add R8,EDE Rn EDE 4 2

add R5,&EDE Rn &EDE 4 2

add #100,TAB(R8) #n x(Rm) 5 3

add &TONI,&EDE &TONI &EDE 6 3

add #1,&EDE #1 &EDE 4 2 RMR©2012


78

Example Cycles Per Instruction

RMR©2012


MSP30 µController

79

S emb t4-arch_cpu

Technology

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arm addresses

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