S emb t5-arch_io

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Maths is not everything

Embedded Systems4 - Hardware Architecture

CPUInput/Output mechanisms

Memory Buses and Aux I/O

Input/Output interfacesPower Management

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Input/OutputMechanisms

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I/O devices

Usual ly includes some non-digital component.Typical digital interface to CPU:

CPUstatusreg

datareg m

echa

nism

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Application: 8251 UART

Un iversa l a synchronous rece i ver transmitter (UART): provides serial communication.8251 functions are integrated into standard PC interface chip.Allows many communication parameters to be programmed.

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Serial communication

Characters are transmitted separately:

time

bit 0 bit 1 bit n-1

no char (marking)

start

stop

...

Serial communication parameters

Baud (bit) rate.Number of bits per character.Parity/no parity.Even/odd parity.Length of stop bit (1, 1.5, 2 bits).

par

8251

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8251 CPU interface

CPUstatus(8 bit)

data(8 bit)

serialport

xmit/rcv

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Programming I/O

Two types of instructions can support I/O:special-purpose I/O instructions;

memory-mapped load/store instructions.

Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O.I/O instructions do not preclude memory-mapped I/O

It is possible to have memory-mapped I/O on a x86 architecture...

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ARM memory-mapped I/O

Define location for device:DEV1 EQU 0x1000

Read/write code:LDR r1,#DEV1 ; set up device addrLDR r0,[r1] ; read DEV1

LDR r0,#8 ; set up value to writeSTR r0,[r1] ; write value to device

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MSP430 memory mapped I/O

Start of flash (0xF000)ORG 0xF000

LED1 EQU BIT3

Reset:mov.b #00001000b, &0x2A ;set port direction

; mov.b #LED1,&P2DIR mov.b #00001000b, &0x29 ;set output to LED

; mov.b #LED1,&P2OUT Stop:

jmp stop

ORG 0xFFFEDW ResetEND

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Peek and poke

Traditional HLL interfaces:int peek(char *location) {

! return *location;

}

void poke(char *location, char newval){

! (*location) = newval;

}

used as:

dev_stat= peek(DEV1);! poke (DEV1, 8);

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Busy/wait output

Simplest way to program device.

Use instructions to test when device is ready.

char *mystring = “ hello world”;char *current_char; current_char = mystring;while (*current_char != ‘\0’) { poke(OUT_CHAR,*current_char); while (peek(OUT_STATUS) != 0); current_char++;}

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Simultaneous busy/wait input and output

while (TRUE) {

! /* read */

! while (peek(IN_STATUS) == 0); /* wait */

! achar = (char)peek(IN_DATA);

! /* write */

! poke(OUT_DATA,achar);

! poke(OUT_STATUS,1);

! while (peek(OUT_STATUS) != 0);/* wait */

! }

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Interrupt I/O

Busy/wait is very inefficient.CPU can’t do other work while testing device.

Hard to do simultaneous I/O.

Interrupts allow a device to change the flow of control in the CPU.

Causes subroutine call to handle device.

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Interrupt interface

CPU

statusreg

datareg m

echa

nism

PC

intr request

intr ack

data/address

IR

CPU and device are connected by CPU bus.CPU and device handshake:

device asserts interrupt request;

CPU asserts interrupt acknowledge when it can handle the interrupt.

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Interrupt behavior

Based on subroutine call mechanism.Interrupt forces next instruction to be a subroutine call to a predetermined location.

Return address is saved to resume executing foreground program.

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Example: character I/O handlers

void input_handler() {! achar = peek(IN_DATA);! gotchar = TRUE;! poke(IN_STATUS,0);}void output_handler() {/* nothing has to be done here as the call to this function implies the char has been sent */

}

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Example: interrupt-driven main program

main() {! while (TRUE) {! ! if (gotchar) {! !! poke(OUT_DATA,achar);! !! poke(OUT_STATUS,1);! !! gotchar = FALSE;

! !! }! !}! }

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Example: interrupt I/O with buffers

Queue for characters:

head tailhead tail

a

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Buffer-based input handler

void input_handler() {! char achar;! if (full_buffer()) error = 1;! else {

achar = peek(IN_DATA);add_char(achar);

}! poke(IN_STATUS,0);/* if buffer was empty force sending */! if (nchars == 1) {

poke(OUT_DATA,remove_char());poke(OUT_STATUS,1);

}}

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I/O sequence diagram

:foreground :input :output :queue

empty

a

empty

b

bc

c

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Priorities and vectors

Two mechanisms allow us to make interrupts more specific:

Priorities determine what interrupt gets CPU first.

Vectors determine what code is called for each type of interrupt.

Mechanisms are orthogonal: most CPUs provide both.

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Prioritized interrupts

CPU

device 1 device 2 device n

L1 L2 .. Ln

interruptacknowledge

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Interrupt prioritization

Masking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete.Non-maskable interrupt (NMI): highest-priority, never masked.

Often used for power-down.

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Example: Prioritized I/O

:interrupts :foreground :A :B :C

B

A,B

C

A

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Interrupt vectors

Allow different devices to be handled by different code.Interrupt vector table:

handler 0

handler 1

handler 2

handler 3

Interruptvector

table head

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Interrupt vector acquisition

:CPU :device

receiverequest

receiveack

receivevector

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Generic interrupt mechanism

intr?N

Y

Assume priority selection is

handled before this point.

Nignore

Y

ack

vector?

Y

Y

Ntimeout?

Ybus error

call table[vector]

intr priority > current priority?

continueexecution

N

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Interrupt sequence

CPU acknowledges request.Device sends vector.CPU calls handler.Software processes request.CPU restores state to foreground program.

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Interrupt Service Routines

Look superficially like a subroutine.

However, unlike subroutinesISR’s can execute at unpredictable times.

Must carry out action and thoroughly clean up.

Must be concerned with shared variables.

Must return using the right instruction

e.g. reti rather than ret in MSP430

ISR must handle interrupt in such a way that the interrupted code can be resumed without error

Copies of all registers used in the ISR must be saved (preferably on the stack)

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Interrupt Service Routines

Well-written ISRs:Should be short and fast

Should affect the rest of the system as little as possible

Require a balance between doing very little – thereby leaving the background code with lots of processing – and doing a lot and leaving the background code with nothing to do

Applications that use interrupts should:Disable interrupts as little as possible

Respond to interrupts as quickly as possible

Communicate w/ISR only through global variables (never through registers!!!)

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Debugging interrupt code

Interrupt-related runtime problems can be exceptionally hard to debug !!!

Common interrupt-related errors include:Failing to protect global variables

Forgetting to actually include the ISR - no linker error!

Not testing or validating thoroughly

Stack overflow

Running out of CPU horsepower

Interrupting critical code

Trying to outsmart the compiler

What if you forget to change/save registers?Foreground program can exhibit mysterious bugs.

Bugs will be hard to repeat---depend on interrupt timing.

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Sources of interrupt overhead

Handler execution time.Interrupt mechanism overhead.Register save/restore.Pipeline-related penalties.Cache-related penalties.

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Input/OutputARM Interrupt Mechanisms

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ARM interrupts

ARM7 supports two types of interrupts:Fast interrupt requests (FIQs).

Interrupt requests (IRQs).

Interrupt table starts at location 0.

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ARM Modes - registers

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ARM interrupt procedure

CPU actions:Save PC.

Copy CPSR to SPSR.

Force bits in CPSR to record interrupt.

Force PC to vector.

Handler responsibilities:Restore proper PC.

Restore CPSR from SPSR.

Clear interrupt disable flags.

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ARM interrupt latency

Worst-case latency to respond to interrupt is 27 cycles (best is ≈ 4 cycles):

Two cycles to synchronize external request.

Up to 20 cycles to complete current instruction.

Three cycles for data abort.

Two cycles to enter interrupt handling state.

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Input/OutputMSP430 Interrupt Mechanisms

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Interrupts

Interrupts preempt normal code executionInterrupt code runs in the foreground

Normal (e.g. main()) code runs in the background

Interrupts can be enabled and disabledGlobally

Individually on a per-peripheral basis

Non-Maskable Interrupt (NMI)

The occurrence of each interrupt is unpredictableWhen an interrupt occurs

Where an interrupt occurs

Interrupts are associated with a variety of on-chip and off-chip peripherals.

Timers, Watchdog, D/A, Accelerometer

NMI, change-on-pin (Switch)39

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Interrupt Flags

Each interrupt has a flag that is raised (set) when the interrupt occurs.Each interrupt flag has a corresponding enable bit – setting this bit allows a hardware module to request an interrupt.Most interrupts are maskable, which means they can only interrupt if

1) enabled and

2) the general interrupt enable (GIE) bit is set in the status register (SR).

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Interrupt Vectors

The address of an ISR is defined in an interrupt vector.

The MSP430 uses vectored interrupts where each ISR has its own vector stored in a vector table located at the end of program memory.

Note: The vector table is at a fixed location (defined by the processor data sheet), but the ISRs can be located anywhere in memory.

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INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT ADDRESS SECTION PRIORITY Power-up External reset Watchdog

PORIFG RSTIFG WDTIFG

Reset 0xFFFE .reset 15, highest

NMI Oscillator fault Flash memory violation

NMIIFG OFIFG ACCDVIFG

Non-maskable 0xFFFC .int14 14

Timer_B3 TBCCR0 CCIFG Maskable 0xFFFA .int13 13

Timer_B3 TBCCR1 CCIFG TBCCR2 CCIFG, TBIFG Maskable 0xFFF8 .int12 12

0xFFF6 .int11 11 Watchdog Timer WDTIFG Maskable 0xFFF4 .int10 10 Timer_A3 TACCR0 CCIFG Maskable 0xFFF2 .int09 9

Timer_A3 TACCR1 CCIFG, TACCR2 CCIFG, TAIFG Maskable 0xFFF0 .int08 8

USCI_A0/USCI_B0 Rx UCA0RXIFG, USB0RXIFG Maskable 0xFFEE .int07 7 USCI_Z0/USCI_B0 Tx UCA0TXIFG, UCB0TXIFG Maskable 0xFFEC .int06 6 ADC10 ADC10IFG Maskable 0xFFEA .int05 5

0xFFE8 .int04 4 I/O Port P2 P2IFG.0 – P2IFG.7 Maskable 0xFFE6 .int03 3 I/O Port P1 P1IFG.0 – P1IFG.7 Maskable 0xFFE4 .int02 2

0xFFE2 .int01 1 0xFFE0 .int00 0

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InterruptsMSP430x2xx Interrupt Vectors

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MSP430F2274 Address Space

Byte8-bit Special Function Registers0x000F0x000016

Byte8-bit Peripherals Modules0x00FF0x0010240

Word16-bit Peripherals Modules0x01FF0x0100256

Word/ByteStack0x05FF

0x02001KBSRAM

Word/ByteProgram Code0xFFBF

0x8000

WordInterrupt Vector Table0xFFFF0xFFC0

32KBFlash

AccessDescriptionAddressSizeMemory

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Processing an Interrupt…

Current instruction completed

MCLK started if CPU was off

Processor pushes program counter on stack

Processor pushes status register on stack

Interrupt w/highest priority is selected

Interrupt request flag cleared if single sourced

Status register is clearedDisables further maskable interrupts (GIE cleared)

Terminates low-power mode

Processor fetches interrupt vector and stores it in the program counter

User ISR must do the rest!44

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Interrupt Stack

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Returning from ISR

MSP430 requires 6 clock cycles before the ISR begins executing

The time between the interrupt request and the start of the ISR is called latency

An ISR always finishes with the return from interrupt instruction (reti) requiring 5 cycles

The SR is popped from the stackRe-enables maskable interruptsRestores previous low-power mode of operation

The PC is popped from the stackNote: if waking up the processor with an ISR, the new power mode must be set in the stack saved SR

Single operand instructions:

Emulated instructions:

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Return From Interrupt

Mnemonic Operation Description PUSH(.B or .W) src SP-2→SP, src→@SP Push byte/word source on stack

CALL dst SP-2→SP, PC+2→@SP dst→PC

Subroutine call to destination

RETI TOS→SR, SP+2→SP TOS→PC, SP+2→SP

Return from interrupt

Mnemonic Operation Emulation Description RET @SP→PC

SP+2→SP MOV @SP+,PC Return from subroutine

POP(.B or .W) dst @SP→temp SP+2→SP temp→dst

MOV(.B or .W) @SP+,dst

Pop byte/word from stack to destination

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Input/OutputPrivileged Modes

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Supervisor mode

May want to provide protective barriers between programs.

Avoid memory corruption.

Need supervisor mode to manage the various programs.MSP430 does not have a supervisor mode.

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ARM supervisor mode

Use SWI instruction to enter supervisor mode, similar to subroutine:

SWI CODE_1

Sets PC to 0x08. Argument to SWI is passed to supervisor mode code.Saves CPSR in SPSR.

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Exception

Exception: internally detected error.Except ions are synchronous with instructions but unpredictable.Build exception mechanism on top of interrupt mechanism.Exceptions are usually prioritized and vectorized.

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Trap

Trap (software interrupt): an exception generated by an instruction.

Call supervisor mode.

ARM uses SWI instruction for traps.

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