EMC-3D Japan/Korea Technical SymposiumApril 23-27, 2007
Page1
VoidVoid--Free Cu Filling Free Cu Filling within High Aspect Ratio within High Aspect Ratio TSVsTSVs
Tom Ritzdorf and Charles Sharbono Semitool, Inc.
40µm diam.,110µm deep vias after CMP40µm diam.,110µm deep vias after CMP
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 2
Outlines
SiP and 3D Packaging
Through-Silicon-Via (TSV) Chip Integration
TSV Copper Filling
ECD fill mechanism
Factors affecting filling profiles
Void-free filling at optimized conditions
Conclusions
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 3
Demands from Consumer Electronics Market
System on Chip
SiP and 3D PackagingMEMS
Bio-InterfacePower Supply
System Complexity
Cos
t / F
unct
ion
Ti
me
to M
arke
t
Source : ITRS
Compared to SoC, SiP offers
- greater flexibility
- shorter time to market
- less development cost.
System in a PackageSystem in a Package
(Multi-chip & 3D packages)
Product complexity ↑Product life cycle ↓
Size, Weight, Cost, and Power ↓Features and Functionality ↑
Incorporation of other circuit elements (MEMS, opto-electronics, and bio-electronics)
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 4
SIP Technologies
Chip in PCB / Polymer single layermulti-layer 3D stack
WL Thin Chip Integration single layerstacked functional layers
Embedded Structure
PoP PiP
Stacked Die wire bond, WB+FCChip to Chip / Wafer flip chip, face to face
through siliconWL 3D stackwafer to wafer (W2W)
Stacked Structure
Substrate:organic laminate, ceramic, glass, silicon, leadframeChip Interconnection:wire bond and/or flip chip
+ passive components integrated into the substratediscrete (CSP, SMD)
Side by Side Placement
TechnologyTechnologyChip / Component Chip / Component ConfigurationConfiguration
Chip in PCB / Polymer single layermulti-layer 3D stack
WL Thin Chip Integration single layerstacked functional layers
Embedded Structure
PoP PiP
Stacked Die wire bond, WB+FCChip to Chip / Wafer flip chip, face to face
through siliconWL 3D stackwafer to wafer (W2W)
Stacked Structure
Substrate:organic laminate, ceramic, glass, silicon, leadframeChip Interconnection:wire bond and/or flip chip
+ passive components integrated into the substratediscrete (CSP, SMD)
Side by Side Placement
TechnologyTechnologyChip / Component Chip / Component ConfigurationConfiguration
Source : ITRS
Need strategies and solutions for test, yield, and rework.
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 5
Benefits of TSV IntegrationTSV electrodes can provide vertical connections that are both the shortest and the most plentiful.Connection length ≈ chip thickness
High density, high aspect ratio, and small pitch connections
RC delays and power consumption are reduced
Therefore, TSV interconnection can overcome the limitations of typical SiP methods.
Source : Fraunhofer-IZM James Lu, RPI, Peaks in Packaging, 2003
EMC-3D European Technical SymposiumJune 25-29, 2007
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VoidVoid--free Filling at Optimized Conditionsfree Filling at Optimized Conditions
0
50
100
150
200
0 20 40 60 80 100
Via Diameter (µµµµm)
Via
Dep
th ( µµ µµ
m)
Feature size tre
nd !
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 7
Requirements for TSV Integration
Robust and precise thinning process flow
Handling concepts for a thin wafer
Electrical interconnects through a thinned wafer
Suitable bonding process : alignment, bonding, and dicing
Via etch : shape, angle, and scallop controlInsulator/Barrier/Seed : conformality and adhesion controlCopper fill : fill robustness and speed controlMetal removal : surface smoothness and over-polish control
Need cooperation with industrial leaders in equipment, materials, and technology.
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 8
Various TSV Filling Methodologies
ECD CuCVD W, Cu,
or Poly-SiConductive Polymer
or Conformal Cu/Polymer
High purity Low resistivity No size/shape limitation
Source : Fraunhofer-IZM Source : IMEC
TodayToday’’s s topictopic
EMC-3D European Technical SymposiumJune 25-29, 2007
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Void-free Filling with Various Dimensions
12µm×100µm
40µm×100µm
5µm×25µm
30µm×110µm
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 10
Seed Continuity
Prerequisites
20µm
Seed Continuity
50µm×225µm
Surface Wetting
EMC-3D European Technical SymposiumJune 25-29, 2007
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Via Filling Profiles
Cu2+ + 2e- → Cu0
Charge Transfer
Mass Transfer
Void formation mechanism : Higher deposition rate near the via mouth due to faster charge and mass transfer, causing pinch-off
12µm×100µm
EMC-3D European Technical SymposiumJune 25-29, 2007
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Potential Variation through a High AR Via
Additive adsorption/desorption behavior is also dependent on local potential.
Factors
- Copper seed layer (thickness and coverage)- Feature dimension- Bath conductivity
67mS/cm 247mS/cm
250µm
Model Parameters
- Uniform seed layer - Constant current density
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 13
Mass Transfer in a High AR ViaModel Conditions : Steady state model fluid velocity, 50µm via diameter
Constant fluid velocity across feature top
200µm
100µm
50µmAR = 4
AR = 2
AR = 1
Convection
Diffusion
50µm
As AR increases, a larger portion of the via becomes diffusion-controlled.
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 14
Via Filling Mechanism
Cu2+ + 2e- → Cu0
Charge Transfer
Mass Transfer
[Cu2+]
[Suppressor][Leveller]
[Accelerator]
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 15
How to Achieve Void-free Filling?
Prerequisites
Seed conformality for uniform charge transfer
Surface wetting for proper mass transfer
Reduce current crowding at the via mouth
Waveform
Bath composition
Reduce mass transfer limitation at the via bottom
Bath LCD
Flow mechanism
Impact of current density?
EMC-3D European Technical SymposiumJune 25-29, 2007
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Reduce Current Crowding at Via Mouth
30µm×110µm Chemical-induced
Waveform-assisted12µm×100µm
DC PR
PR is helpful for high AR, deep vias.
EMC-3D European Technical SymposiumJune 25-29, 2007
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Reduced Current Crowding at Via Mouth : Chemical-induced
Different Organic Set
12µm×100µm
30µm×110µm
AA+S
A+S+L
Increasing accelerator conc. Increasing suppressor conc.
EMC-3D European Technical SymposiumJune 25-29, 2007
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Reduced Current Crowding at Via Mouth: Waveform-assisted
DC
PR
PR cycle time
12µm×100µm
At a fixed amp-time and bath composition
Optimum duty cycles
EMC-3D European Technical SymposiumJune 25-29, 2007
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Reduced Mass Transfer Limitation at Via Bottom
Bath LCD : A higher LCD bath is preferred.
Flow Mechanism : The ion transport within deep vias may not be substantially enhanced by the increased convection. But, a strong flow mechanism is still required for better transfer of organic components.
Increased bath LCD Increased bath LCD
DC PR
EMC-3D European Technical SymposiumJune 25-29, 2007
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Current Density Effect12µm×100µm
40µm×100µm
Current Density
Increases current crowding at the via mouth
Approaches mass transfer limit at the via
bottom
Increasing Current Density
Reduces deposit within the via
EMC-3D European Technical SymposiumJune 25-29, 2007
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0
20
40
60
80
100
120
140
160
0 1000 2000 3000 4000 5000
Feature Cross-Sectional Area (µµµµm2)
Fill
Tim
e (m
in)
Feature Dimension vs. Filling TimeFeature Dimension vs. Filling Time
14×125um
40×100um
5×25um
30×100um
Why is Smaller Feature Dimension preferred?
EMC-3D European Technical SymposiumJune 25-29, 2007
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Filling Time vs. Manufacturability
0
10
20
30
40
50
60
70
80
90
100
0 30 60 90 120 150
Filling Time per Wafer (min)
Cos
t of O
wne
rshi
p ($
)
0
2
4
6
8
10
12
14
16
18
20
Thro
ughp
ut (w
afer
s/ho
ur)
Actual throughput & CoO varies with tool configuration and process conditions. Resist pattern plating will have better overall cost of ownership.
Assumptions1. Hardware : 6 CFD3m and 2 SRD2. Operation : 500 hours/month3. 200mm wafers with no PR pattern4. Fixed current density
14×125um 40×100um
5×25um
30×100um
Manufacturablity
EMC-3D European Technical SymposiumJune 25-29, 2007
Page 23
Summary
Void-free Bottom-up Filling
Copper filling process with robustness and speed is among the most important to make TSV interconnection manufacturable.
Surface wettabilitySeed conformality Bath composition Waveform and current density Flow conditions
Eliminate mass transfer limitations at the via bottom
Reduce current crowding at the via mouth
Prerequisites for proper mass transfer and current distribution