Update in Material and Process Technologies for 2.5/3D IC Dr. Rainer Knippelmeyer CTO and VP of R&D, SUSS Microtec AG
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Temporary Bonding / Debonding as Thin Wafer Handling Solution for 3DIC & Interposers
Device Manufacturing
TSV Processing Temp
Bonding Thinning Post Processing Temp Debonding
Stacking C2C C2W W2W
Thin
Wafer Handling
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Status of Temporary Bonding/Debonding Processes and Materials
Initial R&D
Volume Ramp-up
HVM Line R&D
(Integration)
Industry
Feasibility Yield (Cost) Improvement
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Outline
Latest Insights in Material and Process Technologies for
Interposer and 3D Stacking
4
Introduction: Room Temperature Debonding
Material/Process Optimization & Survey
1
2
Conclusions & Roadmap 3
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
DEBOND METHOD / MATERIAL
SOLVENT RELEASE
THERMAL SLIDE SOLID
STATE LASER RELEASE
MECHANICAL EXCIMER
LASER ASSISTED
SIMPLE CARRIER LOW COO
NO THERMAL STRESSES NO CARBONIZATION
HIGH THROUGHPUT CAPABLE
ROOM TEMPERATURE DEBONDING
SUSS FOCUS
Industry Trend Towards Room Temperature Debonding
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Device Wafer
Add & Prepare
Release or Zoned Layer(s)
Thinned Device
Wafer
Carrier Wafer Attach to Dicing Frame
(optional edge cut / for
ZoneBond® )
Mechanical Debond at
Room Temperature
Clean Device Wafer
Flip Wafer
Bond
Flip Wafer
Temporary Bond
Debond
Carrier Wafer
Spin Coat & Prepare
Adhesive(s)
General Mechanical Room Temperature Debond Process
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Excimer Laser Assisted
Room Temperature Debonding
• Excimer laser debonding Mechanism
– Nanosecond laser pulses break bonds of polymer materials and create gaseous state
– Fast expansion of gas “cuts” material open
• Advantages to Solid State Laser
– No carbonization / thermal stresses
• Flat top beam profile / 10x better stability
no excess energy in substrate
– No laser energy near device
• Laser light absorbed in 200-300 nm layer
– Allows unobscured visible light inspection
• Adhesive only has to absorb in UV (308/248 nm)
– Works on a range of existing adhesives
Device Wafer
Glas Carrier
Laser beam
Adhesive
Absorption
layer
absorption in thin special layer
absorption in first 200-300 nm of adhesive
Device Wafer
Glas Carrier
Adhesive
Glas carrier and wafer separated
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Device Wafer
Add & Prepare
ABSORPTION LAYER
Thinned Device
Wafer
Carrier Wafer Attach to Dicing
Frame
Mechanical Debond /
(Minimal/Zero lift of force)
at Room Temperature
Clean Device Wafer
Flip Wafer
Bond
Flip Wafer
Temporary Bond
Debond
Carrier Wafer
Spin Coat & Prepare
Adhesive(s)
General Laser Assisted Room Temperature Debond Process
Excimer Laser
Treatment (308nm)
( ) Optional
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Outline
Latest Insights in Material and Process Technologies for
Interposer and 3D Stacking
9
Introduction: Room Temperature Debonding
Material/Process Optimization & Survey
1
2
Conclusions & Roadmap 3
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
• Vacuum process compatibility
• Temperature stability ≥ 250C (up to 350C)
• Chemical compatibility
General Adhesive Requirements for Temporary Bonding/Debonding
Application Type of Topography Embedded in Adhesive Adhesive Thickness
Today’s Si TTV Requirements
Thinning / TSV exposure
Pad / RDL 20µm ≤2µm
Chip stacking / Interposer
Cu Nail / Micro Bump (10 - 40µm) 20 - 70µm ≤4µm
Interposer C4 bump (70-80µm) ≥100µm ≤5-7µm
Device Manufacturing
TSV Processing Temp
Bonding Thinning Post Processing Temp Debonding
Stacking C2C C2W W2W
• Easy to de-bond (no thermal stress)
• Easy to clean (no chemical stress)
• Possibility to re-use / recycle carriers
• Total Thickness Variation on Silicon
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Temp. Bonding/Debonding Process Survey
11
Production Readiness
1 : Qualified /used for high volume manufacturing
2: Integration tests in line at institute
3: Qualified by SUSS internal tests
Cost of Ownership
Equipment cost
Process times & cycles
Other consumables:
e.g. Cost of Tape
(Cost of materials)
Performance
Process Latitude
(Survivability / Debondability)
Achievable min. wafer thickness (TTV)
WaferBOND™
ZoneBOND® WSS
“laser free”
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
WaferBOND
™ ZoneBOND
®
WSS
“laser
free”
Other Material Suppliers
Different material classes: • Thermoplastic • Thermoset • Photoset
SUSS Open Equipment Platform and Supported Materials
10 Material suppliers & processes: 9 enable mechanical Debonding 4 enable Laser Asstisted Room Temp. Debonding
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
TTV improvement from 10-15µm down to 2µm for C4 bumped wafers with 70µm bump height and 115µm adhesive thickness
TTV Optimization Example with Thin Materials (TMAT) Adhesive
Before process optimization: bonded stack TTV =10-15µm
After process optimization: bonded stack TTV = 2µm
Adhesive Carrier
Device Bonded stack TTV
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Scanning Acoustic Microscope Images after Bonding and Thinning
SAM image post bond (full
thickness) shows no voids SAM image after thinning
to 50µm shows no defects
•300mm wafers with 8µm bumps, 60µm adhesive
•Si - TTV = 1.3 µm after thinning to 50µm
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Cost of Ownership: Optimization of Cleaning Procedures
Solvent Compability
Influencing Parameters
Process Steps
Nozzle
Flow Rate
Solvent
Dispense Spin Off Rinse Dry
Nozzle
Flow Rate
Time / Spin Speed / Puddle
Time
Spin Speed
Time
Spin Speed
Time
Spin Speed
Number of cycles
Solves Adhesive
Tape Frame
Wafer
Chemical #1 Chemical #2 Chemical #3 Chemical #4
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Cost of Ownership: Example for 8x Improvement of Cleaning CoO
Solvent Glue thickness Cleaning time Consumption of
the solvent
Origin POR
110 µm 100% 100%
Improved POR
110 µm 72% 66%
Comparison of the cleaning time and solvent consumption
Solvent Price per liter Consumption of the solvent
Volume Costs
Origin POR
100% 100% 100% €
Improved POR
30% 66% 12,5%€
Comparison of the solvent consumption and the costs
8 1,5
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Dicing tape integrity critical for results Special resistant tapes increase CoO
Wrinkled tape increases the risk of thin wafer damage during handling
Solvent exposure can lead to substantial tape degradation
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Cost of Ownership reduction: Tape protection allows to use standard tapes for most cleaning chemicals
SUSS thin wafer cleaning module allows to protect the tape and frame
•Good chance to use existing and qualified tapes (cost benefit)
•Higher flexibility for cleaning solvents
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
20
Optimization / Collaboration results:
• Adhesive
• stable at high postprocessing temperatures > 350°C
• Based on mature temporary bonding material composition
• Transparent adhesive allowing optical inspection
• Throughput: > 40wph
• Debonding time < 45sec for 300mm wafer (160mJ/cm2)
High temperature / High Throughput low CoO capable laser assisted debonding
Wafer stack after excimer laser debonding Wafer stack with glass carrier removed Wafer after Cleaning
In collaboration with
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Succesfull process flow integration results at IMEC
Device
Carrier
Device
TTV of 50µm Si wafer
Carrier
Thinned Device Wafer
Temp. Bond Adhesive
Adhesive Thickness TTV after thinning
on 50µm Si
TTV[%] as a function of Adh.
Thickness
A 55µm 3µm 5,5%
A 20µm 2µm 10%
B 100µm 7µm 7%
C 45µm 4µm 8,9%
D 50µm 2µm 4,0%
E 60µm 5µm 8,3%
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Outline
Latest Insights in Material and Process Technologies for
Interposer and 3D Stacking
22
Introduction: Room Temperature Debonding
Material/Process Optimization & Survey
1
2
Conclusions & Roadmap 3
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
0
20
40
60
80
100
Material "A"High Bond
Force
Material "B"High Latitude
ComplexProcess
Material "A"Lower Bond
Force
Material "B"Mechanical
Ideal ProcessFlow
Material "C"Mechanical
Material "C"High Latitude
Material "F"Mechanical
Examples of cost equipment / Maturity for 2.5D / 3D processes
No
rma
lize
d C
ost of E
qu
ipm
en
t / W
afe
r
Cost of Equipment includes: Bonder / Debonder / Device Wafer Cleaner, Carrier cleaning / recycling is not considered
Maturity Qualified or in Production / Process Integration at Institutes / Customer Samples Internal Qual.
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Laser Assisted Debonding vs. Mechanical Debonding
REQUIREMENT MECHANICAL EXCIMER
LASER ASSISTED
DUAL CARRIER PROCESS FLOW (SELECTIVE DEBONDING) *
GLAS CARRIER
SILICON CARRIER
RISK OF LASER ENERGY NEAR ACTIVE DEVICE **
3D
´Memory
Logic
2.5D
Interposer
* Limited Process window/latitude ** Risk can be significantly reduced by proper choice of adhesive/absorption layer
• Both processes suited to 3D and 2.5D requirements • Mechanical debonding seems closest fit to 3D requirements • Laser assisted process originally used only for high performance logic –
now seems closest fit to 2.5D interposer requirements
ROOM TEMP. DEBONDING
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Roadmap: Drivers & Levers
•Choice of Materials
•Material Consumption
•Process Timing and flow
•Equipment optimization
•Bump size and density
•Final device wafer thickness
•Temperature and chemical load
Close collaborations and JDPs with: • Institutes,
•Adhesive and tape manufacturers
•Further TTV Optimization
•Extend room temp. debonding
•New/Improved bond materials
• Leading edge customers
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
Roadmap: SUSS/ITRI: 5µm Ultra Thin Wafer
300mm 50µm thickness with TSV wafer
SUSS XBS300 5µm Ultra Thin Wafer
Update in Material and Process Technologies for 2.5/3D IC
Rainer Knippelmeyer, SUSS Microtec AG
• Trend towards room temperature debonding
–Mechanical debonding mainly 3D processes
–Laser assisted debonding mostly 2.5 D processes
• 10 materials/processes available for room temperature debonding
–4 in or qualified for Volume Manufacturing
–1.5 – 3 x Cost of Equipment reductions in nearterm roadmap
–Main optimization topic: process latitude
• Close collaborations enable roadmap
–Equipment vendors, material vendors
–Leading customers, institutes
Summary
See you next time at:
SUSS TECHNOLOGY FORUM
ASIA 2013
Taiwan, Hsinchu | November 13
China, Shanghai | November 15
Korea November 19