© 2012 Copyrights © Yole Developpement SA. All rights reserved. 3DIC & TSV interconnects 2012 Business update Semicon Taiwan 2012 – [email protected] Infineon Micron Synopsys VTI CEA LETI Xilinx
© 2012
Copyrights © Yole Developpement SA. All rights reserved.
3DIC & TSV interconnects
2012 Business update
Semicon Taiwan 2012 – [email protected]
Infineon
Micron Synopsys VTI
CEA LETI
Xilinx
© 2012 • 2
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Semiconductor chip packaging market evolution
1970s 1980s 1990s 2000s 2010s 2020s
DIP
QFP
LCC
PGA WL CSP
WB BGA
QFN SOT / TSOP
FO WLP
FC BGA / CSP
SiP
PoP / PiP
2.5D interposer
3DIC
Embedded SiP
3D WLP
FO PoP
FO SiP
Advanced
Packaging
Moving to high-
performance,
high-density, low
cost, collective
wafer-level-
packaging
technique
standards
• The pace of innovation in chip packaging industry has never been faster! Today driven by semiconductor company giants (Intel, Samsung, TI, STMicro, TSMC, Qualcomm…)
along with “Top 5” biggest packaging subcontractors (ASE, Amkor, SPIL, STATschippac, PTI…)
© 2012 • 3
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FOWLP ‘Fan-in’ WLCSP 2.5D
Interposers 3D WLCSP
Flip Chip
• This report is focused on the three middle-end technological platforms in which TSV is used
as a vertical interconnect: 3D WLCSP, 2.5D Interposer and 3DIC
Scope of today’s presentation
ST Elpida
Xilinx
3D
FOWLP
Today’s
presentation!
3DIC
© 2012 • 4
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Samsung’s TSV / WLP
in mobile phone CIS
TSV / WLP Reality in Low-End, FSI CMOS Image Sensors
BYD’s CSP camera module
Galaxycore’s 3D WLCSP of
CMOS image sensors
SuperPix’s TSV package in
2MPixels CMOS image sensors Omnivision’s WLCamera with TSV / WLP Sharp’s WLCamera with TSV / WLP
STMicro’s WLCamera with TSV / WLP
Toshiba’s WLCamera with TSV / WLP
OnSemi / Cypress’s3D WLCSP
of medical CMOS image sensor
SK Hynix WLP / TSV
in CMOS image sensors
• Most low-end CIS (CIF, VGA to 2MPixels resolutions) are adopting 3D WLCSP packaging:
© 2012 • 5
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TSV / WLP Reality in High-End, BSI CMOS Image Sensors
• In high-end applications (video cameras, DSC, Smart phones) with > 5-8Mpixel sensor
resolutions, BSI architectures are using ‘front-side’ etched TSV to reach the BEOL metal layers
Toshiba’s redundant TSV interconnects in BSI image sensors
found in Fujifilm camera (Courtesy of Chipworks)
Samsung’s TSV trench TSV in BSI image sensors found in
Galaxy SII Smart phone product (Courtesy of System Plus Consulting, Chipworks)
© 2012 • 6
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TSV Implementation in MEMS Accelerometer
• STMicroelectronics Accelerometer with TSV in MEMS IC
– Device was introduced in 2011 and can be found in Nokia’s mobile phone
Courtesy of System Plus Consulting
TSV
© 2012 • 7
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0
20
40
60
80
100
120
140
Rev
enu
es (
M$
)
2011 global 3D TSV actvity* - Including internal production lines -
3DIC
2.5D Interposer
3D WLCSP
2011 Global 3D TSV activity - Breakdown by top players
* Middle-end activity or revenues including
TSV etching, Via Filling, RDL, Bumping,
wafer test & wafer level assembly
2011 total 3D TSV activity
revenues ~ $340 Million
© 2012 • 8
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PA
Capping IPD Sapphire or
Silicon 3D IPD MOSFET
IGBT & Power MOSFET Power GaN
2012 2014 2016 2018
CIS DSP SOC CIS
BSI CIS
DSP + mem DSP
mem
CIS
SOC CIS
SOC CIS
2010
SOC CIS
2011 2013 2015 2017 2019
3D
WLCSP
FSI
BSI
< 2008 2009
MEMS
ASIC MEMS
Capping
MEMS
ASIC Analog/RF
MEMS Logic
MEMS
Capping
FBAR
Capping
DDR stack Hybrid Memory Cube
NAND Flash stack Wide IO stack
LED
Driver
LED
Driver
LED LED
LED LED LED IPD
FPGA FPGA FPGA FPGA
Analog Digital RF Mem. Analog
Digital ASIC MEMS
Analog
Digital
RF
Mem.
Wide IO FPGA
Wide IO APE
Wide IO
APE
CPU
DDR3 stack
GPU DDR3
Logic
Logic
Logic
3D SiP/SoC
Global 3DIC & TSV interconnects roadmap
MEMS & Sensors
Imaging & Opto
Power,
Analog
& RF
Stacked
Memories
HB-LED
modules
3D SoC
3D SiP Ultimate Heterogeneous
3DIC
© 2012 • 9
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-
2,000,000
4,000,000
6,000,000
8,000,000
10,000,000
2010 2011 2012 2013 2014 2015 2016 2017
Waf
er c
ou
nt
(12
’’e
q.)
Global TSV Chip Wafer Forecast (All 3D Platforms) Breakdown by Segment (12''eq wafers)
3D Stacked NAND Flash
3D Wide IO Memory
Logic 3D SiP / SoC
3D Stacked DRAM
MEMS / Sensors
LED
RF, Power, Analog &Mixed signal
Imaging &Optoelectronics
Yole Developpement © July 2012
Global TSV chip wafer forecast
© 2012• 10
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Micro-bump Pitch = 45µm
Bump Pitch = 40 – 250µm
Why 2.5D glass / silicon interposers are needed?
• 2.5D Glass / Silicon interposers are emerging as key substrate elements for connecting
the nanometer to millimeter worlds in future semiconductor chip packaging assembly
(12-28nm) (5-45um) (Glass / Silicon substrate)
(40-250um)
C4 Bump
(5-100um)
(0,5-5µm)
Wiring /
RDL
(0,4 – 0,8 mm)
BGA balls
BGA
laminate
PCB / PWB
© 2012• 11
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2.5D interposer solution for Large die Logic applications (FPGA, ASICs, DSP, etc…)
PCB
Logic n
Silicon interposer
Logic n+1 Logic n+2 Logic n+3
BGA Laminate
• ‘4 slices’ instead of one die 3D-SOC re-partionned logic design – Increase back of CMOS manufacturing yield (because of smaller die size)
– High density wiring at the surface of the 4 layer copper damascene silicon interposer wafer
breakthrough in COST versus POWER CONSUMPTION versus PERFORMANCE
© 2012• 12
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2.5D interposer solution for Logic + Memory integration (FPGA, ASICs, DSP, CPU / GPU, etc…)
PCB
Memory CPU / GPU Memory
Silicon interposer
BGA Laminate
• Breakthrough in bandwidth & performance versus power consumption – Massive parallel DDR memory integration close to logic IC and interconnected through high density /
high speed silicon interposer wiring layers
– Unprecedented level of computing performance and thermal management possible (side by side)
© 2012• 13
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2.5D interposers for large CPUs / GPUs
• Power 8 by IBM to be based on 2.5D Interposers
• Haswel, Intel GPU on 2.5D interposers for computing with lots of on board
memory and ultra large data bus
IBM Power 7+: four 32nm CMOS multi-core
CPU dies are placed side by side on a
silicon interposer.
(Courtesy of SemiAccuracte.com)
Cross section pictures of an IBM 3D stacked module demonstrator with TSVs in the thinner die
(courtesy of Chipworks)
© 2012• 14
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GPU in 2.5D for gaming console applications
• Sony PS4 (2013) will have a GPU on interposer with a 512-wide data bus
and on interposer memory
– Will probably be an AMD chip. Future gaming platforms will offer 3D imagery, which
requires fast & high bandwidth computing power. 2.5D is unanymously praised as the
solution for this purpose
An interposer module for GPU demonstrator
Courtesy of Global Foundries, 2012
© 2012• 15
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Logic-only 2.5D interposer competing solutions for high performance / large digital single packaged ICs
• Fan-out WLP and fcBGA with copper pillars are likely to take on most of today’s fcBGA market
• Logic-only 3D interposers are only expected to develop for very high I/O density and I/O count processors
Log (unpackaged IC size)
Log (I/O count)
20mm2 50mm2
100mm2 500mm2
100
300
1,000
>5,000
Mobile phone
baseband ICs
Mobile phone
application processors,
low-end CPUs
High-end CPUs,
GPUs
© 2012 • 16
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2.5D Interposer Platform Revenues
• By 2017, we expect 2.5D interposer revenues to reach 14%
of the packaging substrate market value
2010 2011 2012 2013 2014 2015 2016 2017
Organic IC packaging substrate revenues $ 8.3 B $ 8.5 B $ 8.7 B $ 8.8 B $ 9.0 B $ 9.2 B $ 9.4 B $ 9.6 B
Glass/Silicon interposer substrate revenues $ 0.01 B $ 0.02 B $ 0.05 B $ 0.18 B $ 0.42 B $ 0.65 B $ 0.97 B $ 1.36 B
2.5D Interposer technology penetration rate 0.2% 0.3% 0.6% 2.1% 4.7% 7.1% 10.3% 14.2%
0%
5%
10%
15%
0
2
4
6
8
10
12
2.5
D In
terp
ose
r Pe
net
rati
on
rat
e
Rev
enu
es (
B$
)
2.5D Glass & Silicon Interposer Platform Revenues Comparison with laminate substrate industry (B$)
Yole Developpement © July 2012
© 2012• 17
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Qualcomm CPU roadmap: from PoP to 2.5D / 3DIC
• Qualcomm is actively developing the 2.5D interposers & 3DIC architectures
Courtesy of Qualcomm
Mobile applications
Tablet / Gaming / Smart TV applications
© 2012 • 18
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Wide IO memories - Coming Soon! Focus on Samsung’s recent announcement
• Samsung foundry announced it will be ready next year to release 3D TSV
Technology and Wide IO Memory!
– Switching from a conventional PoP approach to 3D stack with wide IO memory will
enable package size reduction by 35%, and power consumption by 50%
– Bandwith is expected to increase by 8
Courtesy of Samsung
© 2012 • 19
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Logic 2.5D / 3D SoC verus SiP packaging roadmap
2010 2011 2012 2013 2015 2014 2016 2017 2018 > 2020 2019
3D-SiP Performance-
driven
3D-SoC Cost &
Performance –
driven
FPGA FPGA FPGA FPGA Analog Digital RF Mem.
GPU DDR3
Analog
Digital
ASIC
MEMS
Analog
Digital
RF
Mem.
Wide IO FPGA
Wide IO APE
Wide IO
APE
CPU
GPU
DDR3 stack
DDR3 stack
CPU DDR3
Logic
Logic
System Partitioning
« Hybrid »
3D-SiP/SoC
3DIC
Smart TV
Set-top box
Network
Data center
Server
Game console
Industrial applications
Tablets
Industrial & networking applications
Smartphones
Ultimate
Heterogeneous 3DIC
« powerpoint concept »
Mobile
© 2012 • 20
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Roadblocks toward 2.5D / 3DIC commercialization in HVM
• There are 5 main challenges ahead for a wide adoption of 3DICs:
– Infrastructure availability & supply chain: availability of a second source
3D packaging service provider is critical before starting any production.
Additionally, key strategic alliances / partnerships between memory suppliers,
Logic IDMs, Foundries and Packaging subcontractors need to be in place for
3D SiP applications involving multiple-party ICs (memory, logic, interposer…)
– I/O standardization between interfaces such as memory / logic / interposer
layers is also critical. Such specifications need to be defined in order to
establish a standardized and flexible supply chain (e.g. of JEDEC initiative for
defining Wide IO memory standards for 3D TSV in consumer applications)
– Thermal management & interconnect reliability: in many applications such as
stacking of DRAM modules, SSD for enterprise market and memory + logic stacking
applications, thermal management is certainly the biggest barrier to entry
for 3D if we cannot manage to dissipate heat well through the whole package
– Shift in the Design / Test method paradigm & system co-design: heterogeneous
functions, packaging, new CAD tools (thermal & mechanical simulation), test
for KGD and new design architectures are required to get the full benefits of 3D
– Cost: depending on end-product, 3D TSV manufacturing cost should be reasonable
and reduced in order to make it widely occurring in cost sensitive applications
Logic
LPDDR3
© 2012 • 21
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TSV manufacturing tool-box Technology Readiness Dashboard
Ready for initial ramp-up
Ready for HVM
Not ready
TSV Middle
Manufacturability TSV
Lithography
TSV
etching TSV isolation
Barrier &
Seed layer TSV filling CMP
Passiv./
UBM &
Bumping
Process performance
(vs technical requirements)
Repetability Uniformity
& process Window
Tool availability & maturity
Throughput & cost of
Ownership
TSV Middle
Manufacturability
Stacking / Bonding
Temporary
bonding to
carrier
Thinning /
grinding
TSV
nailing
Carrier
debonding
Inspection
&
metrology
Testing (probing
& final test) C2C C2W W2W
Process performance
(vs technical requirements)
Repetability Uniformity
& process Window
Tool availability & maturity
Throughput & cost of
Ownership
© 2012 • 22
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Complex IC packaging supply chain (main business models)
System /
Product
Sub-Module /
Sub-systems Design & Assembly
Design of chip & package
Wafer Level
Packaging « Middle -end »
Silicon Manufacturing
« Front-end »
Package Assembly
& Final test « Back-end »
Package substrate
laminate suppliers
Front-end related
materials suppliers
OEMs (Original
Equipment
Makers)
FE related
equipment suppliers
BE Packaging
materials suppliers
BE Packaging
equipment suppliers
Fab-less
IC players
IDMs (Integrated Device Manufacturers)
Wafer foundries
OSATs (Open Source Assembly & Test houses)
Wafer Bumping
houses
Research
Institutes (acting across the
complete supply
chain)
BE assembly & Test houses
WLP houses (no need for traditional substrate)
PWB suppliers (motherboard)
ODM / EMS / DMS
(electronic design &
manufacturing services)
SiP module houses
Passive comp. & SMT materials
SMT equipment
suppliers
SiP design
houses
IP houses (related to packaging,
accross the complete
supply chain)
Test houses
Substrate material suppliers (FR4, BT resin, Cu clad, etc…)
© 2012 • 23
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TSMC’s Integrated Supply-Chain for efficient 2.5D Interposer integration
• TSMC’s vertical integration move from wafer
manufacturing to bumping, packaging, assembly
& test will tackle the supply chain challenge
related to the commercialization of 2.5D/3DIC
modules Altera’s FPGA supported by
TSMC’s CoWoS 2.5D interposer platform
© 2012• 24
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ASE 2.5D silicon interposer platform
– 5/5µm to 10/10µm
Line/Spaces ( supported by
RDL technology)
– 100-150µm thick silicon
– Via diameters of 30-50µm
(DRIE or laser drilled)
– Copper via plating
• ASE (TW) is developing ‘coarse’ type of 2.5D
silicon interposer substrate solution with high
electrical performances
© 2012 • 25
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Emerging 2.5D / 3DIC Open Ecosystems of “Virtual IDMs”
?
?
‘VERTICALLY INTEGRATED’ wafer + package manufacturing foundries
chip / package
Design
‘COLLABORATIVE’ supply-chains between wafer foundries & packaging subcontractors Fab-less / Fab-light
chip companies “VIRTUAL IDM” new ecosystems
FE ‘Middle-end’ BE
pro
fits
pro
fits
$$$$
$$
etch
implant
CVD
PVD
CMP Wafer test
TSV bumping RDL C2W
C2C / C2S underfill
molding Final test
handling thinning
BGA dicing
inspection
cleaning
© 2012 • 26
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Silicon & Glass 2.5D Interposers: Who is doing what?
Wafer
/panel
supply
TSV/TGV
making
Wiring
(BEOL, RDL)
Interposer
test
Bumping
Packaging &
assembly
Final test
Silicon substrate
makers
Glass substrate
makers
IC wafer foundry
MEMS wafer
foundry (or IPD
wafer foundry)
OSATs
PCB
manufacturers
IDMs
New TSMC model
Coarse-pitch
Interposers
Fine-pitch
Interposers
New ASE model
© 2012 • 27
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• The “role sharing” between each party is not obvious – Indeed, the “middle-end” space is almost a ‘zero-margin’ business, while front-end wafer
manufacturing as well as back-end assembly & test remain profitable enough areas for sustainable
business. We estimate that the global 3D TSV semiconductors packaging, assembly and test markets
will reach $9B in business by 2017
‘Middle-end’ versus ‘Back-end’ 2.5D / 3DIC opportunity
2010 2011 2012 2013 2014 2015 2016 2017
Back-end' assembly & test processing value $0.1B $0.2B $0.3B $0.6B $1.3B $2.3B $3.7B $5.8B
Global 'Middle-end' wafer processing value $0.2B $0.3B $0.5B $0.7B $1.2B $1.8B $2.6B $3.5B
-
$1.0B
$2.0B
$3.0B
$4.0B
$5.0B
$6.0B
$7.0B
$8.0B
$9.0B
$10.0B
man
ufa
ctu
rin
g va
lue
(in
B$
)
Global 3D TSV semiconductors packaging, assembly & test market value
Yole Developpement © July 2012
CAGR
81%
46%
© 2012 • 28
Copyrights © Yole Développement SA. All rights reserved.
• It is clear from this picture that the OSAT suppliers have a defined role to play in the future
landscape for 2.5D & 3DIC packages:
– First in the back-end area, where their large infrastructure and expertise in advanced assembly & test
will be key in the successful ramp-up of ever more complex 3D package products
– Secondly, in the ‘middle-end’ area by establishing strategic collaborations with key IDM and wafer
foundries in the IC industry, in order to partner ‘tactically’ while leveraging the high capacity of
investment of these powerful semiconductor chip companies
Taken alone, the back-end space represents a clear opportunity for sustainable growth for major OSAT
suppliers in this emerging “2.0” advanced packaging industry. However, this segment won’t be accessible
without the settlement of a viable ecosystem, including putting the back-end to middle-end processing together.
Expect “vertically integrated” and “collaborative” models to emerge as the most successful in this game!
“Middle-end” place in the future landscape of 2.5D / 3DIC integration
FE wafer manufacturing
2.5D & 3DIC
‘Middle-end’
BE assembly & test
bu
sin
ess
bu
sin
ess
> B12$
~ B6$ etch
implant
CVD PVD
CMP
Wafer test
TSV bumping
RDL / wiring C2W
C2C / C2S underfill
molding Final test handling thinning BGA
dicing
inspection
cleaning
~ B3.5B
“Middle-end” place in the future landscape of 2.5D / 3DIC chip to package manufacturing
A vision of value distribution by 2017
inspection W2W
© 2012 • 29
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Thank you very much for your attention!
Visit us during Semicon’Taiwan 2012 @ Booth #1327