Built in self test for 3DIC

Built-in Self-Test/Repair Scheme for TSV-Based Three-Dimensional Integrated Circuits

Hung-Yen Huang#1, Yu-Sheng Huang#2, and Chun-Lung Hsu #3 #Department of Electrical Engineering, National Dong Hwa University

1, Sec. 2, Da Hsueh Rd., Shou-Feng, Hualien, 974, Taiwan, R.O.C. [email protected] [email protected]

[email protected]

Abstract—This paper presents a built-in self-test/repair (BISTR) scheme for through-silicon via (TSV) based three-dimension integrated circuits (3D ICs). The proposed BIST structure focuses on the testing of a specific defective TSV by using a critical value of threshold. Then, the test results from BIST will be delivered to the BISR structure for repairing the defective TSV. Additionally, a parallel processing approach is presented of the proposed BISTR scheme to speed up the operations of test and repair. Experimental results demonstrate that the proposed BISTR scheme can achieve the good performance in repair rate and yield with little area overhead penalty. Keywords—3D IC, TSV, BIST, BISR, area overhead, yield.

I. INTRODUCTION Recent development in technology has enabled the

fabrication of a single chip with multiple device interconnect layers (wafers) stacked on each other. This novel approach is commonly referred to as the 3D ICs [1]. Comparing with the traditional two-dimensional (2D) ICs, 3D integration has the potential to offer significant performance and functional benefits such as interconnection enhancement, high device integration density, wire length reduction, and the ability to combine disparate heterogeneous technologies [2].

3D integration technology is one of the fastest growing IC design directions that offer flexible and low cost packaging solutions. A number of technologies for 3D ICs have been explored in recent years, including transistor stacking, die-on-wafer stacking, wafer stacking, and chip stacking [3]. Among these technologies, the wafer stacking approach is one of the most promising avenues for the implementation of high-performance yet inexpensive 3D ICs. Wafer stacking relies on TSVs for vertical connectivity, guaranteeing low latency, low power dissipation, and, if needed, extremely high densities of vertical wires [4]. Additionally, TSVs allow fine pitch, high density and high compatibility with the standard CMOS process. However, currently available processes for TSV fabrication have relatively low yield compared to the standard 2D processes [5]. That is to say, as designers embrace the TSV-based 3D IC technology, the unwanted loss in yield and performance may occur if the via fails to make proper

connection. Thus, the test techniques and design for testability (DFT) solutions for TSV-based 3D ICs design have become an important issue in the research community.

A BISTR scheme for TSV-based 3D ICs testing is presented here to increase the yield improvement with respect to random complete or partial open defects. The proposed BISTR scheme relies on a number of redundant TSVs allocated to a group of TSVs to timely repair the defective TSVs for yield improvement in 3D ICs design applications. By using the proposed TSV-based BISR scheme, a significant yield improvement can be achieved with minimal impact of circuits and low area overhead required for testing. The remainder of this paper is organized as follows. Section II discusses the challenges of 3D ICs testing. The defect models of a TSV for testing requirement are also addressed in this section. The proposed TSV-based BISTR scheme for 3D ICs and corresponding test strategy are presented in Section III. Performance evaluation results, including those of repair rate, yield improvement and area overhead are discussion in Section IV. Finally, Section V gives the conclusions.

II. TEST CONSIDERATIONS In traditional IC manufacturing, wafers are probed and

individual dies tested before they are packed. However, the designers are confronted with new challenges before bonding wafers in the 3D integration [6]. The yield of 3D ICs can be increased if the designers can bond pretested dies, or if the designers can sort the wafers first and stack matched dies on top of each other. The TSVs are key components of 3D ICs and are used for providing power, as well as clock and functional signals. Additionally, TSVs also provide test access to logic blocks on different layers. In other words, TSVs make up a key test infrastructure. Any defective TSVs will prevent test access of certain logic blocks. Under the circumstances, even a single TSV defect between any two layers can void the entire chip stack, reducing the overall yield.

To guarantee the full functionally of 3D TSV interconnects, the designers have to take the precaution of implementing redundancy and self-repairing mechanisms for each TSV, especially those for transmitting signals. According to the

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testing requirement, the defect model of a TSV must to be clarified and defined. Generally, the primary defects for the TSVs are misalignment and random open defects [7]. Misalignment refers to unsuccessful wafer alignment prior to and during wafer bonding process. Generally, misalignment is caused by shifts of bonding pads with respect to their nominal positions. An electrical model of misalignment defect of a TSV between two stacked vias is shown in Fig. 1. The contact resistance, in Fig. 1 is related to the quality and area of bonding. In case of misalignments, i.e., top wafer shifts along the x or y axes or a small rotation, the bonded area decreases. Thus, the contact resistance, contR is modelled as a variable resistance to represent this phenomenon. Since misalignments are generally caused by the unavoidable shift of bonding pads with respect to their nominal position, using large square pads twice as wide as standard pads can improve misalignment tolerance by an order of magnitude [8].

wR

wC

2viaR

viaC

2viaR

i-th layer

j-th layer

contR

2viaR

viaC wC LoadC

wR2viaR

In

Out

TSV

TSV Pad

IP

IP

IP

wR

wC

2viaR

viaC

2viaR

i-th layer

j-th layer

contR

2viaR

viaC wC LoadC

wR2viaR

In

Out

TSV

TSV Pad

IPIPIP

IPIPIP

IPIPIP

Fig. 1 The electrical model of misalignment defect of a TSV.

On the other hand, random (complete or partial) open

defects affect single vias or a small area of the interface because of failure mechanisms such as dislocations, O2 trapped on the substrate, void formation, or even mechanical failures in TSVs [9]. Generally, a complete via open defect leads to a complete broken net, while a partial defect increases the resistance of the interconnection. As the technology shrinks, vias become more and more sensitive to variations by cut misalignment, electron migration, and thermal stress induced voids. In other words, random open defects comprise a variety of unpredictable physical phenomena related to the thermal compression process used in wafer stacking.

Since the number of TSVs embedded in a 3D IC is generally high, a single defective TSV can greatly affect the probability of a failure chip resulting in the yield loss. This paper proposes a TSV-based BISTR scheme to effectively detect and repair the defective TSVs for yield improvement with little area overhead.

III. PROPOSED BISTR SCHEME A TSV-based BISTR scheme that increases the assembly

yield for 3D ICs design is illustrated in Fig. 2. From Fig. 2, a

number of redundant TSVs in spared TSV unit is allocated to a group of TSVs. If one of the TSVs is detective, it is replaced by one of the redundant TSVs. In other words, if a failure occurs at a TSV, the remaining TSVs are shifted to the neighboring ones, so a defective TSV is always repaired by a neighboring TSV. This will decrease the detour path, reduce routing complexity and loading.

Controller

Match Reg./Decoder

Signature Reg.

AnalyzerDetecting circuit

Spared TSVBISR

BIST

Fig. 2 The proposed BISTR scheme.

A. Built-In Self-Test In the proposed BISTR scheme, BIST is composed with

detecting circuit, signature register, analyzer and controller for defective TSVs detection. The main component in detecting circuit is test pattern generator (TPG), which consists of linear feedback shift register (LFSR) and administers the transmit of the test pattern Vt. When the BIST is switched to test mode, the test pattern will delivered to all of the TSVs in a row simultaneously. After the test pattern transmits through TSVs, the output response will be sent to an analyser to compare with the test pattern and output response. If the amplitude of comparison result is larger than a threshold value, the TSV should be determined as a defective TSV. On the contrary, the fault occurred in TSV can be tolerance.

The definition of the threshold value in this paper is based on the theory of noise margin. In the design of digital circuit, noise margin is used to assess the ability of anti-noise. In other word, noise margin represents the ability of noise tolerance in digital circuit. According to the definition of ideal noise margin, the threshold used in this paper is defined as Vt / 2. Additionally, the defective TSVs will be labelled and then which positional information will stored in the signature register. In order to reduce the count of registers, the data of test results should be encoded before storing. Moreover, the area will also be reduced by reason of saving the register. After BIST finished the test in a row, the controller will command the BIST process the test procedure to the next row. The labelled positional information and trigger signal will be transmitted to BISR under the command of controller.

B. Built-In Self-Repair The major utility of BISR is to repaire the defective TSVs

which determined by BIST. The BISR include controller, match register/decoder, TSV mapping unit and TSV spared unit. When the controller in BISR receives the trigger signal

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from BIST, the repair procedure will be started immediately. After match register/decoder receives the labelled positional information from signature register via controller in BIST, the information should be decoded first to acquire the real location of defective TSVs. According to the decoded labelled positional information, TSV mapping unit will repair the defective TSVs by the method of shifting and replacing. Fig. 3 indicates the repair method in this paper. If there has any defective TSV in Fig. 3, the multiplexer will isolate the defective TSV by labelled positional information, and switch the signal to the neighboring TSV. In other word, BISR uses the method to repair the TSV by replacing and shifting, the signal through the defective TSV originally will be switched to the neighboring TSV. And the other TSV will follow the method to shift the signal, until the spared TSV replaces the function of the boundary TSV.

TSV Spare Unit

TSVs

IN_A

IN_B

IN_C

IN_D

OUT_A

OUT_B

OUT_C

OUT_D

Top layer Bottom layer

Fig. 3 The repair method in BISR.

TSV spare unit disposes amount of redundancy TSVs in

BISR, the count of spared TSVs have effect on the performance of overall BISR scheme. Moreover, the yield of 3D IC will be influenced. In this paper, the parallel processing had been used in the BISTR scheme. By using the parallel processing, BIST and BISR can process the test and repair procedure at a time, but not at the same row. For example, when BISR repair the n th− row, BIST will test the ( 1)n th+ − row simultaneously. The parallel processing will reduce the processing time of BISTR scheme, and the circuit under test (CUT) can return to normal mode in a short time.

IV. EXPERIMENTAL RESULTS 3D FPGAs are used as CUT to evaluate the performance of

the proposed BISTR scheme. The three 2D FPGA benchmark e64-4lut, tseng and apex4 are partitioned into 3D structure by three-dimensional place and route (TPR) tool, the size of 2D benchmark FPGAs, e64-4lut, tseng and apex4after will be partitioned into 12 12 2× × , 23 23 2× × and 26 26 2× × , respectively.

A. Repair Rate The repair rate is defined to evaluation the performance of

BISR [10]. Repair rate represent the ability to repair the defective TSV in our design. The equation of repair rate will be defined as follow:

# of repaired TSVs

Repair rate = # of faulty TSVs

(1)

In this paper, all of the defective TSVs will be repaired if

the redundancy TSVs are enough. For example, if there exist two defective TSVs in the row and exist two or more redundancy in the row, the defective TSV will be repaired and the repair rate is 100%. On the other hand, if the number of defective TSVs more than redundancy TSVs, some of defective TSVs may not be repaired. Table I shows the evaluation results of repair rate for the benchmark apex4. Table I clearly indicates that the more redundancy TSVs existence, the higher repair rate can be achieved.

TABLE I

REPAIR RATE EVALUATION

Benchmark: apex4 (26 × 26 × 2)

1 5 10 15 20 25

1 100% 20% 10% 6.67% 5% 4%

5 100% 100% 50% 33.33% 25% 20%

10 100% 100% 100% 66.67% 50% 40%

15 100% 100% 100% 100% 75% 60%

20 100% 100% 100% 100% 100% 80%

25 100% 100% 100% 100% 100% 100%

FaultyTSVSpared

TSV

B. Yield Under the fabrication technology of 3D IC at present, the

yield of 3D IC is still low. The main reason is that the faults occurred in the fabrication processing of TSVs. In a word, TSV is the main factor to the yield of 3D IC. Generally, yield can be effectively estimated by the Poisson distribution. The yield is in connection with the area of the circuit (AIC), the defect density of the circuit (dIC) and the repair rate (R) [11]. The equation of yield can be defined as follow:

Yield = (1 )RIC IC IC ICA d A de e− −+ − (2) In Table II, the benchmark circuit apex4 adds different

number of redundancy TSVs, the yield will be improved as repair rate increased. However, the area overhead comes with the redundancy TSVs. The balance between area overhead and yield is an important issue. Designer can trade off overhead against yield according to the consideration of cost and the probability of defective TSVs.

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TABLE II YIELD ESTIMATION

Yield before repair: 65.15%

Benchmark: apex4 (26 × 26 × 2)

1 5 10 15 20 25

1 100% 72.12% 68.64% 67.47% 66.89% 66.54%5 100% 100% 82.58% 76.77% 73.86% 72.12%10 100% 100% 100% 88.38% 82.58% 79.09%15 100% 100% 100% 100% 91.29% 86.06%20 100% 100% 100% 100% 100% 93.03%25 100% 100% 100% 100% 100% 100%

FaultyTSVSpared

TSV

C. Area overhead To evaluate the testing scheme, area overhead is an

important issue. In this paper, the BISTR scheme based on the three 3D FPGA benchmarks by using TSMS 0.18 μm processing. The area overhead is computed by estimating the area of three benchmarks and the proposed BISTR scheme. Different size of benchmark will acquire diverse design, so the area of BISTR in each benchmark will be different. Table III indicates that the area overhead of BISTR scheme is ideally low. The larger size of benchmark need lower area overhead than smaller one. It means that the proposed BISTR scheme is suitable for high density circuit design. The count of register and redundancy TSVs are the critical factor to influence the area overhead.

TABLE III

AREA OVERHEAD ESTIMATION

Based on TSMC 0.18μm processing

BenchmarkSize Overhead

2D 3D BIST BISR Totale64-4lut 17×17 12×12×2 3.12% 6.45% 9.57%

tseng 33×33 23×23×2 1.47% 3.31% 4.78%

apex4 36×36 26×26×2 1.28% 2.92% 4.2%

D. Parallel processing In 3D IC, not all the rows have least one defective TSV.

The rows location on 3D IC should be tested first, and determine whether the row process the repair procedure or not. Actually, the repair procedure may not be executed in some rows. In this paper, the test and repair procedure will be aimed at a row of TSVs. The TSVs in the same row will be tested at a time, and BISR will be turned on after the test procedure. Significantly, the row will process the repair procedure, and the next row also processes the test procedure simultaneously. The two procedures processed at a time, called parallel processing. Fig. 4 shows that the processing period under parallel processing and non-parallel processing. The performance in parallel processing is almost twice better than non-parallel processing. It can reduce the test and repair time and let the CUT return the normal mode in short time.

0

50

100

150

200

250

0 10 20 30 40 50 60 70 80 90 100

proc

essi

ng p

erio

d (T

)

# of TSVs per row

parallel

non-parallel

Fig. 4 The processing time under parallel processing and non- parallel processing.

V. CONCLUSIONS This paper proposes a BISTR scheme for TSV-based 3D

ICs faulty detection and repair applications. The defective TSVs can be detected by a specific threshold value of the proposed BIST structure. Also, the defective TSVs can be effectively isolated and repaired by a neighboring TSV of the proposed BISR structure. Experimental results and discussion show that the great yield improvement can be achieved with little area overhead penalty by using the proposed BISTR scheme.

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