Tallinn University of Technology
Founded as engineering college in 1918, TTU acquired university status in 1936.
TTU has about 9000 students and 1209 employees, offering engineering and economics diploma studies, bachelor, master and doctorate degree programmes.
Academic part of the university is organised into 8 faculties, 30 departments and 108
chairs, 7 centres and 9 affiliated institutions.
Raimund Ubar
Computer Engineering Department
Research Topics
• Computer science: Decision Diagrams • Test Pattern Generation
Hierarchical ApproachesDefect-Level Testing
• Simulation of Circuits and SystemsFault Simulation (SAF, functional faults, delays)Dynamic (multivalued) Simulation
• Built-In Self-TestHybrid BISTFunctional BIST
• Hardware accelerators for Fault Simulation
European projectsHistory (1992-2000):
• TEMPUS: Digital Design based on PLDs (1992-95)• EUROCHIP (1993 -1996) - EUROPRACTICE (1996 -)• PECO: EEMCN - East European Microelectronics Cooperation
Network (1993-96)• COPERNICUS: FUTEG - Functional Test Generation (1994-
97)• ESPRIT: ATSEC - Advanced Test Generation and Testable
Design Methodology (1994-96)• COPERNICUS: SYTIC - System Design Training (1996-98)• COPERNICUS: VILAB - Microelectronics Virtual Laboratory for
Cooperation in Research (1998-2002)
Current European Projects
• FRAMEWORK V: REASON - Research and Training Action for System On Chip Design (2002-2004)
• FRAMEWORK V: eVikings II - Establishment of the Virtual Centre of Excellence for IST RTD in Estonia
• SOCRATES 2 Thematic Network Project THEIERE -Thematic Harmonisation in Electrical and Information EngineeRing in Europe
• SOCRATES 2 Thematic Network Project ECET - European Computing Education and Training (2002-2004)
• EUROPRACTICE
Our Partners
TTU LIU
Darmstadt
KTH
USA: Michigan U
Costa Rica
Stuttgart Grenoble
Torino
East- and
Middle-Europe
Jonköping
Dresden
Ilmenau
TTU cooperates with about 20-30 universities
Indonesia
Kharkov
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3Modules or subcircuits are represented as word-level DD structures
Logic Synthesis Scripts
Design Compiler(Synopsys Inc.)
Gate LevelDescriptions
SSBDD Synthesis
SSBDD Modelsof FUs
Hierarchical ATPG
RTL Model(VHDL)
FULibrary(VHDL)
FULibrary(DDs)
RTL DD Synthesis
Test patterns
RTL DDModel
Hierarchical Test Generation Tool
Test Generation
BIST Simulation
Methods:DeterministicRandomGenetic
Methods:BILBOCSTPStore/Generate
Design Test
Levels:GateMacro
Fault Simulation
Methods:Single faultParallelDeductive
Fault Table
Fault models:Stuck-at-faultsStuck-opensDelay faults
Test Optimization
Fault Diagnosis
Fault Location
Turbo-Tester Tool Set
Hybrid BIST for Multiple Cores
SoC
C3540
C1908 C880 C1355
Embedded Tester C2670
Test accessmechanismBIST BIST
BISTBISTBIST
Test Controller
TesterMemory
Embedded tester for testing multiple cores
Optimized Multi-Core H-BISTPseudorandom test is carried out in parallel, deterministic test - sequentially
Applet for Learning RT L Test
ForFor learninglearning problems problems ofof RT- RT-level digital level digital design design andand test test::
• Design of Design of data path and data path and control pathcontrol path
• TTradeoffs radeoffs between speed between speed & HW cost& HW cost
• RT-level RT-level simulationsimulation
• Fault Fault simulationsimulation
• Test Test generationgeneration
• DFTDFT and and BISTBIST
Virtual Lab: Tool integration
Behavioral levelVHDL description
(EAS/IIS)
High-level
RTL VHDLdescription
High-level DDmodel
HierarchicalATPG(TTU)
Test patterns exchange interfaceFunctional test
(EAS/IIS)
Logicsynthesis
Gate-levelEDIF
EDIF-SSBDDconverter(TTU)
SSBDD model
High-levelVHDL description
(EAS/IIS)
Turbo Tester
1 2
3 4
5 6
VHDL-DDconverter(TTU)
EDIF-ISCASconverter(TTU)
8
synthesis
ISCAS-SSBDDconverter(TTU)
9
ISCAS netlist
ISCASbenchmarks
DefGen(IIN)
10 Universitysoftware
11(TTU)
Schematicentry
7
CommercialCAD software
MOSCITOUSER
(EAS/IIS)
Cooperation with Fh-IIS, DTU, LIU, IISAS, WUT
Proposal: Ingredients of SoC test
1. Functional test to test the system (WP1)
2. BIST, embedded test for IP cores (WP3)
System-on-a-Chip
IP core
Functional test (system test)
BIST, test control, test access
Tallinn University of Technology
• WP1. High-level modeling and simulation Methods for automated generation of functional
test at the system-level for verification purposes.
We have previous experience in: High-level modeling and simulation
High-level test pattern generation
Design error identification at the logic level.
Tallinn University of Technology
• WP3. Setting up a Virtual IP library Solutions for automated synthesis of the test
infrastructure to IPs. Novel hybrid BIST strategies
Functional BIST
Web based e-learning tools for teaching IP test
standards like Boundary scan and P1500.
Artec Design Group
• Artec Design Ltd. founded in 1998 is a successful Estonian SME empoying more than 30 people.
• In 2001, the company was selected to top ten in the Central European Technology Fast list.
• The field of the Artec company is designing hardware, ASICs, embedded software and factory information systems.
• The company has been involved in a number of national and European level research projects.
Artec Design Group
• VPNow: an IP core for cryptographic network processing. – It allows any system with PCI interface to connect using
the IPSec encryption standard. – Possible to send new, ipv6 internet protocol packets via
existing ipv4 networks and vice-versa.
• A network-ready, full-function compact 486 motherboard with an award-winning Single Component Computer MachZ.