ECEN 248 Lab8_report

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Lab 8: Introduction toSequential Logic

Deanna SessionsECEN 248-511

TA: Priya Venkatas

Date: October 30, 2013


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Objectives:This lab is where we will learn about sequential logic circuits. This includes learning aboutlatches and flip-flops and adding the element of time delays into the circuit. This gets to a morereal-life application of the circuits because time delays end up being a large portion of intricatecircuits and it is important the proper information is at the right place at the right time. The

concept of a synchronous circuit has been talked about in previous labs, but we have not reallycared about time delay up until this point and now we will account for timing with a clock signal.This lab also introduces our first technical usage of latches in which we include a clock and amaster-slave layout of the flip-flop circuit.

Design:Below are all of the source codes from the lab with comments included:

//sr_latch.v `timescale 1 ns/ 1 ps`default_nettype none

module sr_latch( Q, notQ, En, S, R); //defining inputs and outputsoutput wire Q, notQ; //outputs of Q and ~Qinput wire En, S, R; //inputs of an enable bit, set, and reset

wire nandSEN, nandREN; //internal wires

nand #2 nand0(Q, nandSEN, notQ); //NAND gates with time delays of 2 nsnand #2 nand1(notQ, nandREN, Q);nand #2 nand2(nandSEN, En, S);nand #2 nand3(nandREN, En, R);

endmodule

//d_latch//for the #4 just change #2 to #4`timescale 1 ns/ 1 ps`default_nettype none

module d_latch(Q, notQ, En, D); //defining inputs and outputs

input wire D, En; //input of data and enableoutput wire Q, notQ; //outputs Q and ~Q

wire nandDEN, nandNotDEN, notD; //internal wires

not #2 not0(notD, D); //NOT gate to have an inverse of the datanand #2 nand0(Q, nandDEN, notQ); //NAND gates with time delay of 2 ns (or 4 ns for second test)nand #2 nand1(notQ, nandNotDEN, Q);nand #2 nand2(nandDEN, D, En);nand #2 nand3(nandNotDEN, notD, En);

endmodule


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//d_flip_flop.v `timescale 1 ns/ 1 ps`default_nettype none

module d_flip_flop(Q, notQ, Clk, D); //defining inputs and outputs

output wire Q, notQ; //outputs of Q and ~Qinput wire Clk, D; //inputs of a clock and data

wire notClk, notNotClk; //internal wireswire Q_m;wire notQ_m;

not #2 not0(notClk, Clk); //NOT gate to have an inverse clocknot #2 not1(notNotClk, notClk); //NOT gate to have an inverse inverse clock

d_latch master(Q_m, notQ_m, notClk, D); //Master D Latchd_latch slave(Q, notQ, notNotClk, Q_m); //Slave D Latch that follows the Master

endmodule

//new d flip flop that works with my test bench `timescale 1 ns/ 1 ps`default_nettype none

module d_flip_flop(Q, notQ, Q_m, notQ_m, Clk, D); //Defining inputs and outputs

output wire Q, notQ, Q_m, notQ_m; //Gives internal answers as outputs as wellinput wire Clk, D; //inputs of clock and datawire notClk, notNotClk; //internal clock wires

not #2 not0(notClk, Clk); //NOT to have different timed clocknot #2 not1(notNotClk, notClk);

d_latch master(Q_m, notQ_m, notClk, D); //Master D Latchd_latch slave(Q, notQ, notNotClk, Q_m); //Slave D Latch

endmodule

//d_latch_behavioral `timescale 1 ns/ 1 ps`default_nettype none

module d_latch_behavioral( //Defining inputs and outputsoutput reg Q,output wire notQ,

input wire D, En);always@(En or D) //Called whenever the is an Enable or Data

if (En) //If Enable bit is highQ=D; //Then Q is equal to the data

else //anything else (Enable is low)Q=Q; //Q is equal to whatever Q was previously

assign notQ = ~Q;endmodule


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//d_flip_flop_behavioral `timescale 1 ns/ 1 ps`default_nettype none

module d_flip_flop_behavioral( //defining inputs and outputsoutput reg Q,output wire notQ,input wire D,input wire Clk

);

always@(posedge Clk) //If the clock is on a positive edge it latches to dataQ


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input [7:0] numTests;

if(passed == numTests) $display ("All tests passed");else $display("Some tests failed");

endtask

// Inputsreg D;reg Clk;

// Outputswire Q;wire notQ;wire Q_m; //these wires had to be added to match my codewire notQ_m;

reg [7:0] passed;// Instantiate the Unit Under Test (UUT)d_flip_flop uut (

.Q(Q),

.notQ(notQ),

.Clk(Clk),

.D(D),

.Q_m(Q_m), //I had to add these variables to match with my code

.notQ_m(notQ_m));

/*generate clock signal*/always

#40 Clk


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//adder_2bit_tb `timescale 1ns / 1ps

module add_2bit_tb;//a test bench does not have any ports of its own!

/* Input nets */reg [1:0] A; //these are regs because they are modified inreg [1:0] B; //a behavioral block

/* Output nets */wire [1:0] Sum; //these are wires because they will be drivenwire Carry;//by the inantiated module

/* Instantiate the Unit Under Test (UUT) */adder_2bit uut ( //this is a different way

.A(A), //to instantiate a module.

.B(B), //the nice thing about this style

.Sum(Sum), //is that the order does not matter!

.Carry(Carry)//notice the ports are in a different order!);

/*-this is a behavioral block which is executed only once! **-the statements within this behavioral block are executed **-sequentially because we are using blocking statements **-an '=' sign within a behavioral construct is considered a** blocking statement. We will talk more about this later...*/

initialbegin

/* Initialize inputs*/ A = 0;B = 0;

#25; //just delay 25 ns{A,B} = 4'b0000; //stimulate the inputs#25; //wait a bit for the result to propagate//here is where we could put a check to see if the results//are as expected!if({Carry, Sum} != 3'b000)//you could put your own message here

$display("Ah crap... something went wrong here...");else

$display("Hey! The UUT passed this test vector...");//let's do it again with a different input...{A,B} = 4'b0001; //stimulate the inputs#25; //wait a bit for the result to propagate

//check outputif({Carry, Sum} != 3'b001)$display("Your own message here...");else

$display("Test vector passed!!!");{A,B} = 4'b0010; //stimulate the inputs

#25;if({Carry, Sum} != 3'b010) //One of these statements had to be made for each binary possibility



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$display("Hey! The UUT passed this test vector...");{A,B} = 4'b0010; //stimulate the inputs#25;if({Carry, Sum} != 3'b010)








$display("Hey! The UUT passed this test vector...");{A,B} = 4'b0110; //stimulate the inputs#25;if({Carry, Sum} != 3'b011)//you could put your own message here


$display("Hey! The UUT passed this test vector...");{A,B} = 4'b0111; //stimulate the inputs#25;

if({Carry, Sum} != 3'b100)//you could put your own message here$display("Ah crap... something went wrong here...");else




$display("Ah crap... something went wrong here...");else$display("Hey! The UUT passed this test vector...");

{A,B} = 4'b1010; //stimulate the inputs#25;if({Carry, Sum} != 3'b100)//you could put your own message here


$display("Hey! The UUT passed this test vector...");{A,B} = 4'b1011; //stimulate the inputs


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#25;if({Carry, Sum} != 3'b101)//you could put your own message here










$display("Hey! The UUT passed this test vector...");

$stop;end

endmodule

Results:The results below are the waveforms that were created by running the source code found in thedesign section with the test benches that had been previously made (some of which had to bemodified.) The bottom of the screen in each waveform demonstrates that all of the tests were

passed and the waveform itself displays the time delay that was being demonstrated in many ofthe circuits. Each of the waveforms turned out much like I had expected and the circuits thatwere run multiple times with different time delays proved to show the time delay accurately.


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Figure 8.1 : SR Latch 2ns

Figure 8.2 : SR Latch 4ns


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Figure 8.3 : D Latch

Figure 8.4 : D Flip Flop


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Figure 8.5 : D Flip Flop with all 6 outputs

Figure 8.6 : D Flip Flop Behavioral


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Figure 8.7 : D Latch Behavioral

Figure 8.8 : 2-Bit Adder


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Figure 8.9 : 2-bit Adder with Amended Test Bench

Figure 8.10 : Synchronous Adder


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Figure 8.11 : Synchronous Adder at 20 ns Timescale

Conclusion:Questions:

1. Source code shown in design section2. Waveform diagrams shown in results section.3. Questions throughout lab:

a. Now, change the 2 uni t delays in your code to 4 units and run the test benchagain . Explain the resul ts of the simu lation.Using the 4 ns delay caused the Q and notQ results to be delayed by 4ns insteadof 2 ns and the R, S, and En bits stayed the same as they were from the 2 nssimulation. This makes sense because the inputs do not have the time delayapplied to them, the time delay comes through the circuit and the outputs are theones affected.

b. Simulate your D ip - op using the d ip op tb.v le in the course directory. Add the internal nets within your D ip - op to the waveform and examine thewaveform af ter r estar ting the simul ation. Do the latches behave as expected?Why or why not?The latches behave as expected when the internal nets have been added.

c. Compare the waveforms you captured from the behavioral Verilog(d_latch_behavioral.v and d_fl ip_f lop_behavioral.v) to those captured f rom thestru ctural Veri log. Are they diff erent? I f so, how? The main difference is the time it took to start receiving data for Q and notQ. It


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was significantly faster in the behavioral Verilog than it was in the structuralVerilog. Also, the D Latch had no time delay in the behavioral, but a significantdelay in the structural.

4. Compare the behavioral description of the synchronous adder found in the testbench code with the combination of structural and dataflow Verilog you used in the

lab assignment. What are the advantages and disadvantages of each? Which to youprefer and why? The advantage to using the behavioral description is that it is very concise and to the

point because it uses one statement that then decides what kind of output it is going to berather than having to go through each specific answer and check it. In structural anddataflow Verilog it is precise, but efficiency is lost because it has to read for each specificoutput rather than just paying attention to the output behavior as a whole. I prefer

behavioral Verilog when it comes to this because it makes for nicer looking code thatworks efficiently.

5. Based on the clock period you measured for your synchronous adder, what would

be the theoretical maximum clock rate? What would be the effect of increasing thewidth of the adder on the clock rate? How might you improve the clock rate of thedesign? The timescale that the circuit can be reduced to and still work is 20 ns which works at a50MHz clock rate. Increasing the width of the adder would cause the clock rate to drop

because it has to work with more inputs than previously and this would result in more ofa time delay which causes a drop in clock rate. Improving the clock rate of the designwould be best executed by decreasing the time delay in the circuit by simplifying thecircuit to less gates or by using gates with less time delay.

Student Feedback:1. I liked that this lab was clear and to the point while also having enough questions in it

allowing for me to actually learn what I was doing. I feel like I am learning Verilog in anefficient way and using the knowledge that I already have in order to build upon. It wasnice to see the differences between structural and behavioral circuits again and write myown test bench parts.

2. Nothing about the lab manual was unclear.3. Keep it exactly as it is. This lab works so nicely with the preceding labs.

ECEN 248 Lab8_report

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ECEN 248 Lab8_report