ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dept. of Electrical and Computer Engineering.

ECEN 248: ECEN 248: INTRODUCTION INTRODUCTION

TO DIGITAL TO DIGITAL SYSTEMS DESIGNSYSTEMS DESIGN

Dept. of Electrical and Dept. of Electrical and Computer EngineeringComputer Engineering

Describing Circuit Describing Circuit Functionality: InverterFunctionality: Inverter

Basic logic functions have symbols.Basic logic functions have symbols. The same functionality can be represented The same functionality can be represented

with with truth tablestruth tables·· Truth table completely specifies outputs for all Truth table completely specifies outputs for all

input combinations.input combinations. The above circuit is an inverter.The above circuit is an inverter.

An input of 0 is inverted to a 1.An input of 0 is inverted to a 1. An input of 1 is inverted to a 0. An input of 1 is inverted to a 0.

A Y

0 1

1 0

Input Output

A Y

Symbol

Truth Table

The AND GateThe AND Gate

This is an AND gate. This is an AND gate. So, if the two inputs signalsSo, if the two inputs signals

are asserted (high) the are asserted (high) the output will also be asserted.output will also be asserted.Otherwise, the output willOtherwise, the output willbe deasserted (low).be deasserted (low).

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

A

BY

Truth Table

The OR GateThe OR Gate

This is an OR gate. This is an OR gate. So, if either of the twoSo, if either of the two

input signals are input signals are asserted, or both of asserted, or both of them are, the output them are, the output will be asserted.will be asserted.

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

AB

Y

The NAND GateThe NAND Gate

This is a NAND This is a NAND gate. It is a gate. It is a combination of combination of an AND gate an AND gate followed by an followed by an inverter. Its truth inverter. Its truth table shows this.table shows this.

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

AB

Y

The NOR GateThe NOR Gate

This is a NOR gate. It is a This is a NOR gate. It is a combination of an OR gate combination of an OR gate followed by an inverter. Itfollowed by an inverter. It’’s truth s truth table shows thistable shows this

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

AB

Y

The XOR Gate (Exclusive-The XOR Gate (Exclusive-OR)OR)

This is a XOR gate. This is a XOR gate. XOR gates assert their outputXOR gates assert their output

when exactly one of the inputswhen exactly one of the inputs

is asserted, hence the name.is asserted, hence the name. The switching algebra symbolThe switching algebra symbol

for this operation is for this operation is , i.e., i.e.

1 1 1 = 0 and 1 1 = 0 and 1 0 = 1. 0 = 1.

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

AB

Y

ECEN 248ECEN 248

Introduction to Digital Introduction to Digital Design LabDesign Lab

Dept. of Electrical and Dept. of Electrical and Computer EngineeringComputer Engineering

Lab DetailsLab Details http://ece.tamu.edu/~ysy6529 Lab PoliciesLab Policies Issue of Components (Room 111A)Issue of Components (Room 111A) ––

Before Lab ClassBefore Lab Class Structure of Lab - Breadboarding and Structure of Lab - Breadboarding and

VerilogVerilog Tips & Tricks of BreadboardingTips & Tricks of Breadboarding Prelab & Postlab DeliverablesPrelab & Postlab Deliverables Feedback FormFeedback Form

Some Important Rules Some Important Rules

Deliverables:Deliverables: Prelabs (typed, short and concise) are due at the Prelabs (typed, short and concise) are due at the

beginning of each lab. All your designs should be ready. beginning of each lab. All your designs should be ready. Get TAs help during office hours, if you need help on your Get TAs help during office hours, if you need help on your design.design.

Postlabs are due at the beginning of next lab.Postlabs are due at the beginning of next lab. Download, Print and Keep the following:Download, Print and Keep the following:

Lab Manual: Lab Manual: Syllabus, Lab Policy Document- Breadboard tip & tricksSyllabus, Lab Policy Document- Breadboard tip & tricks Lab detailsLab details

Appendix A, BAppendix A, B MiscMisc

Labs stay open till 9:00PM. Use free lab times to complete Labs stay open till 9:00PM. Use free lab times to complete the lab work. Arrange meeting with TA for any help.the lab work. Arrange meeting with TA for any help.

Instruments in the LabInstruments in the Lab1.BreadBoard1.BreadBoard

Line ofPins ShortTogether

GroundLine

PowerLine

IC’s should beplaced across

the splitSplit 1

Split 2

VerticalDirection

HorizontalDirection

PARTITION 1

PARTITION 2

PARTITION 3

PARTITION 4

ICnotch

These 2lines are

not shorted

These 2lines are

not shorted

Instruments in the LabInstruments in the Lab

2.Multimeter2.Multimeter 2.Oscilloscop2.Oscilloscopee

Instruments in the LabInstruments in the Lab

4.Power Supply4.Power Supply

Please talk to the TA if there is any doubt regarding Please talk to the TA if there is any doubt regarding the use of instruments. A detailed description of the use of instruments. A detailed description of each instrument is given in the Tips and Tricks of each instrument is given in the Tips and Tricks of Breadboarding Section.Breadboarding Section.

For IC pin numbers, refer to Appendix AFor IC pin numbers, refer to Appendix A

Lab # 1 in BriefLab # 1 in Brief

Study of Standard GatesStudy of Standard Gates Study the standard 2-input gates given in manualStudy the standard 2-input gates given in manual

Inverter Transfer CharacteristicsInverter Transfer Characteristics Plotting the input vs output voltage for an inverterPlotting the input vs output voltage for an inverter

Ring OscillatorRing Oscillator A ring of inverters as a clock signalA ring of inverters as a clock signal Use 5 inverters back to back as shown in ManualUse 5 inverters back to back as shown in Manual

Lab # 2: Logic Minimization and K-Lab # 2: Logic Minimization and K-MapsMaps

Details and HintsDetails and Hints

a

b

c

d

e

f

g

a

b

c

d

e

fg

ProfitComputer

SevenSegmentDriver

Seven-SegmentDisplay

H

I

S

CP0

P1

P2

A

B

C

D

1. Draw three K-Maps, one for each output for the Profit Computer based on the information in the Farm problem

2. Connect BCD to Seven Segment as shown

3. Connect Seven Segment Display

DeadlineDeadline

First week:Postlab of Lab # 1, part1 is due in class next week.

Prelab for Lab # 2 is due in class next week.

Second weekPostlab of Lab # 1, part2 is due in class next week.