Fall 2018 ECEN 248: Introduction to Digital Logic design Sections: 301, 302, 303 Lecture: MWF, 12:40PM -1:30PM, ZACH 241 Lab: All sections meet in CVLB 418 (NOT ZACH 333): Sec 519 W 6PM – 8:50PM; Sec 520 R 8AM – 10:50AM; Sec 521 R 11:10AM – 2PM; Sec 522 R 2:20PM – 5:10PM; Sec 523 R 5:30PM – 8:20PM Course Description and Prerequisites Introduction to Digital Systems Design. (3-3). Credit 4. Combinational and sequential digital system design techniques; design of practical digital systems. The covered topics are listed at the end of this syllabus. Prerequisite: MATH 152 and PHYS 208 with a grade of C or better. Learning Outcomes or Course Objectives A student who successfully fulfills the course requirements will have demonstrated the ability to convert desired system functionality into a digital design. Specific learning outcomes include the following: (1) ability to analyze and design combinational logic circuits, (2) ability to analyze and design sequential logic circuits, (3) ability to design high-level digital systems using Register-Transfer Level (RTL) design, and (4) utilize the Verilog hardware design language, logic simulation, and Field Programmable Gate Array (FPGA) technology to implement combinational, sequential, and RTL-based digital systems. Instructor Information Dr. Sam Villareal, Senior Lecturer, Department of Electrical and Computer Engineering WEB 218D [email protected]TR, 2PM – 4PM and by appointment 979-862-6334 Textbook: Digital Design with RTL Design, VHDL, and Verilog, 2nd Edition 2011, by Frank Vahid, John Wiley & Sons. ). The textbook is required. Exams are open book and notes, but no electronics. You will have to print textbook sections for the exam if you have an electronic version of the textbook Laboratory Manual: Available online through eCampus (ecampus.tamu.edu) Grading Policy In-Class Assignments: 10% (2 team problems and 1 individual quiz; assigned each class with no Exam or Scheduled Review) Team Projects: 7% 2 Exams: 38% (18% Exam1 Sep 26, 2018; 20% Exam2 Oct 31 2018) Final Exam: 20% (10:30AM – 12:30PM Dec 10, 2018) Laboratory: 25% The two exams (9/26/18 and 10/31/18) and the final exam (12/10/18) will be open book and open notes. While the final exam will be cumulative, 70% of the final will be on material subsequent to the second exam (i.e., 10/31/2018 through 12/5/2018). No electronic devices are allowed in Exam I. The only electronic device allowed during Exam II and the Final Exam is a calculator. Please put your cell phone, smartphone, smartwatch, laptop, etc. in your backpack during the exam. The two exams will be in-class and are on the schedule. The Final Exam is at the scheduled time for final exams (December 10, 10:30AM – 12:30PM). Note: ALL EXAMS & LABS ARE REQUIRED.
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Fall 2018
ECEN 248: Introduction to Digital Logic design
Sections: 301, 302, 303
Lecture: MWF, 12:40PM -1:30PM, ZACH 241
Lab: All sections meet in CVLB 418 (NOT ZACH 333):
Sec 519 W 6PM – 8:50PM; Sec 520 R 8AM – 10:50AM; Sec 521 R 11:10AM – 2PM;
Sec 522 R 2:20PM – 5:10PM; Sec 523 R 5:30PM – 8:20PM
Course Description and Prerequisites Introduction to Digital Systems Design. (3-3). Credit 4. Combinational and sequential digital system design
techniques; design of practical digital systems. The covered topics are listed at the end of this syllabus.
Prerequisite: MATH 152 and PHYS 208 with a grade of C or better.
Learning Outcomes or Course Objectives
A student who successfully fulfills the course requirements will have demonstrated the ability to convert desired
system functionality into a digital design. Specific learning outcomes include the following: (1) ability to
analyze and design combinational logic circuits, (2) ability to analyze and design sequential logic circuits, (3)
ability to design high-level digital systems using Register-Transfer Level (RTL) design, and (4) utilize the
Verilog hardware design language, logic simulation, and Field Programmable Gate Array (FPGA) technology to
implement combinational, sequential, and RTL-based digital systems.
Instructor Information
Dr. Sam Villareal, Senior Lecturer, Department of Electrical and Computer Engineering