\u003ctitle\u003eFast and simple modeling of non-rectangular transistors\u003c/title\u003e

Fast and simple modeling of non-rectangular transistors

Jen-Yi Wuu*a, Fedor G. Pikusb, Malgorzata Marek-Sadowskaa

aElectrical and Computer Engineering Dept, University of California, Santa Barbara, CA 93106 bMentor Graphics Corporation, 8005 SW Boeckman Rd, Wilsonville, OR 97070

ABSTRACT

As CMOS feature size scales down to 65nm and below, challenges for device and circuit manufacturability are emerging. As commonly seen in real designs, devices with distorted gate shapes and rough line-edges are manufactured despite the applications of aggressive resolution enhancement techniques (RET). It has been shown that such irregular gates could introduce significant extra leakage current. Existing tools and device models cannot handle non-rectangular geometries. Therefore, it is critical that a modeling flow capable of handling such irregular devices is developed and smoothly integrated into the post-lithography delay and leakage circuit analysis process. Previously proposed methods either model an irregular transistor as two different rectangular devices, one for on and the other for off state analyses; or they are difficult to be implemented. In this paper, we propose a new modeling approach that serves as a fast and simple solution to this problem and overcomes these drawbacks. We found that by adjusting both gate length and width of the equivalent device, a single equivalent rectangular device can be determined. Through TCAD and SPICE simulation experiments, we demonstrate that our model can accurately capture both on and off currents of the modeled non-rectangular gate device. The average error of our modeling approach is 1.6% for Ion and 7.5% for Ioff.

Keywords: Non-Rectangular Gate Device, Equivalent Device, Modeling

1. INTRODUCTION As the aggressive scaling of feature size continues, various effects due to sub-wavelength photolithography are having prominent influence on the quality of printed silicon images. Many resolution enhancement techniques (RET) have been developed to suppress or compensate for these effects and to improve the quality of the printed images. However, the limitations of RETs and the random variations in the process steps make printing high quality silicon images extremely difficult. Figure 1 shows the layout of a transistor and its simulated silicon image. Although we intend to produce a rectangular transistor, a non-rectangular gate (NRG) shape transistor is obtained. This raises several problems. Current standard device models, such as BSIM, assume rectangular devices only. They do not allow one to supply an NRG shape as an input. If the drawn dimensions of a rectangular shape are used, large discrepancies are observed between the simulated and actual values. Previous studies [4] showed that the NRG shapes cause significant increase in leakage current while saturation current is slightly affected. Therefore, methodologies must be developed for an accurate post-lithography circuit performance analysis.

Figure 1. Layout view (left) and simulated post-lithography image (right) of a device.

*[email protected]; phone 1 805 893 5678.

Photomask Technology 2008, edited by Hiroichi Kawahira, Larry S. Zurbrick, Proc. of SPIE Vol. 7122, 71223S · © 2008 SPIE · CCC code: 0277-786X/08/$18 · doi: 10.1117/12.801541

Proc. of SPIE Vol. 7122 71223S-12008 SPIE Digital Library -- Subscriber Archive Copy

Various recent works address the problem of NRG transistor modeling. Gate slicing and equivalent gate length (EGL) methods are used in [1] to capture the behavior of the NRG gate in on and off states. Gate slicing method is used to compute the current of the NRG device. The equivalent gate length method maps the computed on or off current to an equivalent device suitable for on or off state simulations. The drawback of this method is that it produces two equivalent devices: the ON EGL device for timing simulations and the OFF EGL device for leakage simulations. When it is difficult to determine whether a device is in on or off state, applying this method could be problematic. Besides, the impact of edge effects, such as the inverse narrow-width effect (INWE), is not addressed in this work. In [2] the authors improve the current computation method by considering the location-dependent threshold variation caused by the edge effects. However, this work is still based on the EGL framework; therefore, it suffers from the same drawbacks as mentioned above: it produces two different equivalent devices. In addition, this method requires the characterization of the edge regions in which the threshold variation becomes prominent. In some SPICE models, such as the one we use in our experiments, which was supplied by a semiconductor foundry, very narrow devices cannot be simulated since they are not allowed by design rules and therefore excluded from the model. In such cases, this method cannot be applied. In [3], the authors develop a current-modification based method to obtain a unified non-rectangular device model. Additional model cards are introduced to adjust the device according to its gate shape. However, this method increases the circuit complexity and its implementation is complicated. In [4], a gate-voltage dependent model of equivalent gate length is developed. Though the model is validated by Technology Computer Aided Design (TCAD) simulations, it requires source code inside the device simulator to be modified, which complicates the implementation.

In this paper, we present a modeling flow which computes an equivalent rectangular device for an NRG device. In contrast to the previous works based on EGL method, we determine only one equivalent device which can accurately capture both on and off currents. This greatly simplifies the post-lithography circuit simulation process, since it is not required to determine whether a device would be in on or off state. That same equivalent device replacing the modeled NRG device would be in place for both the on and off state analyses. In addition, the proposed modeling flow is very simple to implement and efficient in applications. A rectangular device characterization must be performed once for all the NRG devices sharing the same process. The characterization step requires only rectangular device current data, which may be obtained easily from SPICE or TCAD simulations. In this work, we also validate the modeling flow through TCAD and SPICE simulations. As demonstrated in TCAD experiments, the average error of our modeling approach is 1.6% for Ion and 7.5% for Ioff.

2. OVERVIEW OF PROPOSED MODEL Current SPICE models, such as BSIM, can only work for rectangular devices. Our modeling approach aims at deriving a single, equivalent rectangular device for an NRG device. By representing NRG devices as equivalent rectangular ones, we are capable of efficiently performing post-lithography simulations. Besides, it is desirable that for each NRG device one equivalent device is used for both delay and leakage analysis. Our model achieves this goal. In the earlier work [1], only equivalent gate length is computed while the equivalent gate width assumes the dimension of the silicon-printed image. Such an approach produces two equivalent devices: one for delay analysis and one for leakage analysis. Different from the earlier works, we adjust both the equivalent gate length and width. Using our approach, only one equivalent device, that is robust for both delay and leakage analysis, is created.

The proposed modeling approach consists of two steps. First, for a given process, a library is built to characterize the rectangular devices. This step is done only once for all devices sharing the same process that we wish to model. Second, for a specific NRG device, given its gate contour obtained from lithography simulator, we determine its equivalent rectangular dimensions. The key step here is estimating of the on and off currents of the NRG device. Once the estimated currents are obtained, the equivalent rectangular device can be determined from the library we built in the first step. Figure 2 illustrates the overview of the modeling approach.

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StepI

Figure 2. Overview of modeling approach. Le and We denote the equivalent gate length and width.

3. MODELING APPROACH In this section, the two steps of the modeling flow are described in detail.

3.1 Rectangular Device Characterization and Library Building

Collecting rectangular device data is important for the characterization of the correlation between device drain current (Ids) and device length (L) and width (W). Organizing such correlation in a structured way helps the process of mapping current back to a rectangular device. To express Ids as a function of L and W we first plot figures of Ids versus L or W. Then, we generate the functions according to the observed curves. The coefficients describing the functions can be stored in a library, to be used for computing equivalent rectangular devices in a later step.

Figure 3. (a) Ion-W plot. (b) Ioff-W plot. In both plots, L ranges from 60nm (top line) to 70nm (bottom line). The unit on y axis

is not shown due to the confidentiality of the calibrated SPICE model.

Figure 3 shows the plots of NMOS drain current versus device width. Figure 3(a) shows the on current (Ion), and Figure 3(b) shows the off current (Ioff). The data is obtained via SPICE simulations using a calibrated 65nm model from a semiconductor foundry. The correlation between Ids and W is very close to perfect linear. However, Ids is not perfectly proportional to W. If the width of a device is doubled, the device does not necessarily produce twice as large current. Effects causing that current is not linearly proportional to W, of which inverse narrow width effect (INWE) is one, account for such behavior.

According to the linear correlation between Ids and W observed, we express Ids as a function of L and W, as:

( , ) ( ) ( )dsI L W L W Lα β= × + (1)

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=a(L)

w

For each fixed L value, the coefficient α(L) denotes the slope of the line in the Ids-W plot and β(L) denotes the y-intercept of the same line. In this way, we can express Ids(L,W) for all rectangular devices by computing α(L) and β(L) over a range of L values. For each L value, α(L) and β(L) can be computed at two points of W, W1 and W2, using equations (2) and (3).

2 1

2 1

( , ) ( , )( ) ds dsI L W I L WLW W

α −=

− (2)

1 1( ) ( , ) ( )dsL I L W L Wβ α= − × (3)

Conceptually, α(L) represents the current produced per unit width from a very wide device, and β(L) represents the current offset due to effects which are not proportional to W. The idea of α(L) and β(L) is illustrated in Figure 4.

Figure 4. α(L) is the slope of the line, representing the current produced per unit width from a very wide device. β(L) is the y-intercept of the line, representing the current offset due to effects which are not proportional to W.

Two lookup tables are built, one for Ion and one for Ioff. Each table contains L as the key and α(L) and β(L) as the values. In this way, we maintain only one parameter, L, as the key in the library. This keeps the library one dimensional, which greatly improves the computational efficiency of determining in the later step the equivalent device length and width.

Note that in Figure 3 there is a “bend” at W=0.3um. This is because the model is calibrated to real silicon data and binned according to W. Devices of different widths may have different layout details such as contact counts, which result in such “bends” in the Ids-W curve. However, within each model bin, the linear correlation between drain current and device width remains. Also note that the model does not support devices in which W < 120nm since such devices violate the design rules corresponding to the model.

3.2 Derivation of Equivalent Rectangular Device

The derivation of the equivalent rectangular device consists of two steps: device current estimation and computation of equivalent gate length (Le) and width (We). These two steps are described in sections 3.2.1 and 3.2.2.

3.2.1 Device Current Estimation

We develop a device current estimation method based on the gate slicing and considering the effects non-linear to device width. The estimated device current is needed in the next step of computing the dimensions of the equivalent device.

Gate slicing is a widely used method to estimate the current of an NRG device [1-4]. Its accuracy has been validated using 3D TCAD simulations [5]. However, it is also noted in [5] that for narrow-width transistors, effects non-linear to device width, such as INWE, have non-ignorable influence on device current and increase the error of the gate-slicing-based estimations. Consequently, we modified the gate slicing method to include an extra term which compensates for such non-linear effects.

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DrinfedN/\ I/if

Figure 5. The NRG device contour is broken into parallel slices in order to estimate its current.

Gate slicing method breaks an NRG device into N parallel, independent slice transistors, whose currents are added together to approximate the NRG device current. Assume that N slices have the same width ΔW=Wtotal/N, where Wtotal is the total width of the NRG device. Figure 5 illustrates the idea. Each slice Si is approximated using a rectangle with dimensions Li and ΔW. The estimated current in the gate slicing method, Islicing, can be computed according to (4):

1 1( ) ( , )

N N

slicing ds i ds ii i

I I S I L W= =

= = ∆∑ ∑ (4)

Applying the concept of α(L), (4) can be re-written as:

1 1( , ) ( )

N N

slicing ds i ii i

I I L W L Wα= =

= ∆ = × ∆∑ ∑ (5)

Motivated by [6], which shows that INWE is modulated by channel length, we define the term of edge offset current, Ioffset, as:

1

1 ( ( ) ( ))2offset NI L Lβ β= +

(6)

Ioffset as a current component determined by the L1 and LN, which are the lengths of the first slice S1 and the last slice SN.

Adding (5) and (6) together, the estimation of an NRG device’s drain current, Iest, becomes:

1

1

1( ) ( ( ) ( ))2

N

est i Ni

I L W L Lα β β=

= × ∆ + +∑ (7)

We used (7) and the lookup tables built in Step 1 to estimate the on and off current of the NRG device, denoted as onestI

and offestI .

Note that it is flexible and acceptable to adopt a different current estimation method in our modeling flow since it is independent of the other modeling steps.

3.2.2 Computation of Equivalent Device Length and Width

Once the estimated on and off currents ( onestI and off

estI ) are obtained, computation of equivalent device length and width (denoted as Le and We) for the equivalent device is straightforward. Solving equation (3) and (4) together yields Le and We:

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DOXD4D5 06

( ) ( )onest on e e on eI L W Lα β= × + (8)

( ) ( )off

est off e e off eI L W Lα β= × + (9)

The equations can be efficiently solved using the lookup tables and interpolations in a numerically way. In all our experiments, only one unique solution is yielded for each NRG device, and the solutions can be found within seconds.

4. VERIFICATION EXPERIMENTS In this section, we verify our modeling approach through 3D TCAD and SPICE simulations.

4.1 TCAD Verification Experiments

We verified our entire modeling approach on a 3D TCAD simulation platform. A commercial 3D TCAD process and device simulator, Synopsys Sentaurus [7], were used in our experiments. The TCAD setup and device structure in [8] were taken as reference points since it contains a structure with nano-scale gate length (50nm) and features device-surrounded shallow trench isolation (STI). Six NRG devices based on a parameterized structure, shown in Figure 6, were used as the test cases. Only half the structure is shown in Figure 6, since it is symmetric to the other half. The parameters of the six NRG devices are listed in Table 1. Figure 6 also shows the 3D device structure with doping profile.

(a) (b) (c)

Figure 6. (a), (b)Two parameterized structures used in our TCAD experiments as test cases. (c) 3D device structure with doping profile.

We simulated rectangular devices at two widths (W1=200nm and W2=300nm) and built the library over a range of L values, as explained in Section 3.1. We applied equation (7) to obtain the estimated current of the NRG devices, Iest. The TCAD simulated current of the NRG devices is denoted as INRG. After the equivalent rectangular device was computed, we simulated its current, denoted as Ieq. In Table 2, we compare Iest, INRG, and Ieq. The errors shown for Iest and Ieq are computed against INRG. The Ids-Vgs plots of device G1 for INRG, Iest, and Ieq are shown in Figure 7. The results show excellent agreement among the estimated and TCAD simulated currents over the entire range of Vgs. The average modeling error is 1.6% for Ion and 7.5% for Ioff. The nature of this error will be discussed in Section 5.

Table 1. Parameters for NRG test cases. For all cases, Wprinted=250nm and Dox=80nm.

Unit:nm G1 G2 G3 G4 G5 G6 D1 20 40 60 -- -- -- D2 40 40 40 -- -- -- D3 65 45 25 -- -- -- D4 -- -- -- 0 20 40 D5 -- -- -- 40 40 40 D6 -- -- -- 85 65 45 Lg 65 65 65 64 64 64

Lneck 57 57 57 -- -- -- Lbulge -- -- -- 70 70 70

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Se-OS

4.Se-OS

4e-OS

3.Se-OS

3e-OS

2.Se-OS

2e-OS

1.Se-OS

le-OS

Se-O6

le-04

le-OS

le-06

le-07

le-OS

le-09

le-lO

le-1 10.6

Vgs (V)

Figure 7. Ids-Vgs plots of device G1 for INRG, Iest, and Ieq. A log-scale y axis is added to the right side so that the Ioff part is

more visible.

Table 2. Comparison of results from TCAD experiments.

On/Off State

Gate INRG (A)

Iest (A)

Iest Error (%)

Ieq (A)

Ieq Error (%)

G1 9.236E-5 9.096E-5 1.51 9.042E-5 2.10 G2 9.390E-5 9.293E-5 1.03 9.252E-5 1.47 G3 9.580E-5 9.490E-5 0.94 9.212E-5 3.84 G4 8.938E-5 8.873E-5 0.73 8.860E-5 0.87 G5 8.802E-5 8.773E-5 0.33 8.726E-5 0.86

On

G6 8.688E-5 8.674E-5 0.17 8.710E-5 0.25 G1 3.406E-11 3.790E-11 11.27 3.876E-11 13.80 G2 4.478E-11 4.828E-11 7.81 4.924E-11 9.96 G3 5.494E-11 5.865E-11 6.76 5.670E-11 3.20 G4 2.312E-11 2.352E-11 1.73 2.346E-11 1.47 G5 2.088E-11 2.136E-11 2.32 2.032E-11 2.68

Off

G6 1.861E-11 1.921E-11 3.22 2.116E-11 13.70

4.2 SPICE Verification Experiments

In addition to TCAD experiments, we verified our modeling approach via SPICE simulations using a calibrated 65nm NMOS model supplied by a foundry. We demonstrate that SPICE model alone is sufficient to apply our model, which is very fast and simple.

Eight NRG devices, whose contours are obtained from lithography simulations, are utilized as test cases. The nominal L value is 70nm. The contours are carefully generated such that they resemble the common irregular gate shapes seen in real designs. The contours are shown in Figure 8. M1 and M2 are contours with almost no irregularity and very close to rectangles. M3 and M4 have a “neck” (section with lengths less than the nominal value) near the right end. M5 through M8 have a “bulge” (section with length greater than the nominal value) at either end. The contours are sliced 1nm wide. The statistics of the slices of each contour are shown in Table 3.

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RI I

Figure 8. Gate contours of test cases. Poly contours are horizontally oriented, and active contours are vertically oriented.

Table 3. Property of the test cases for SPICE experiments.

Gate Avg Li (nm) Li Stdev (nm) Min. Li (nm) Max Li (nm) M1 70.91 0.82 69.87 73.22 M2 71.11 0.91 70.02 73.71 M3 67.82 4.02 60.00 71.98 M4 68.19 3.85 60.50 72.74 M5 71.38 3.35 69.00 85.13 M6 71.54 2.14 69.52 79.42 M7 71.49 3.33 68.47 91.25 M8 71.76 3.85 68.26 93.77

We applied our modeling flow on these test contours. After the equivalent rectangular device is obtained, we feed it back to SPICE to get its current, Ieq. In Table 4, we show the error of Ieq, compared with the estimated current Iest in both on and off states. Note that since we cannot know the current of a NRG device through SPICE simulation, we take Iest as the target for comparison, assuming that it is accurate.

In addition, we also applied an EGL-based method on these test cases. The same estimated currents, onestI and off

estI , are fed into iterations of SPICE simulations to obtain the EGL values for on and off states, denoted as Lon and Loff, which satisfy the following conditions:

( , )on onest ds on printedI I L L W W= = =

( , )off offest ds off printedI I L L W W= = =

In Table 4, we also included the error of ( , )off

ds on printedI L L W W= = compared to offestI and ( , )on

ds off printedI L L W W= = compared

to onestI in Table 4.

The results revealed that, on contours that are close to rectangular, the EGL-based method works reasonably well for both on and off states. However, when the contours exhibit greater irregularity, Lon cannot be used for the off state and Loff cannot be used for the on state. For example, in the case of M8 shown in Table 4, Lon has 20.23% error on Ioff. On the other hand, our model shows that one equivalent rectangular device is capable of capturing both on and off current of an NRG device throughout all the test cases. As shown in Table 4, the average error of our model for Ioff and Ion are 0.29% and 3.25%, respectively. With our model accurately capturing both on and off currents of NRG devices, the post-lithography circuit delay and leakage analysis can be unified, improving the efficiency of performance analysis.

M1

M2

M3

M4

M5

M6

M7

M8

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0

-5e.07

-le.06

-1.Se-06

-206

-2.5e.06

-3e-06

-3.Se-06

-1e.060 0.2 0.4 0.6 0.8 1 1.2

G 1(1 NRG' slicing)

G2( I NRG slicing)

—•:— G3( I NRG slicing)

I =3(L=57nm)offset

Table 4. Accuracy of our method and EGL-based method via SPICE simulations.

Our Method EGL-based Method Gate Le

(nm) We

(um) Ioff Error

with (Le , We)

(%)

Ion Error with

(Le , We) (%)

Wprinted (um)

Lon (nm)

Ioff Error with

(Lon ,Wprinted) (%)

Loff (nm)

Ion Error with

(Loff ,Wprinted) (%)

M1 70.86 0.2010 0.35 0.03 0.2002 70.39 3.17 70.86 0.34 M2 71.00 0.2011 0.36 0.05 0.2005 70.63 2.63 71.03 0.25 M3 66.24 0.2620 0.12 0.02 0.2657 67.66 10.95 66.37 1.19 M4 67.09 0.2609 0.10 0.01 0.2642 68.44 10.03 67.21 1.07 M5 70.48 0.2089 0.34 0.04 0.2055 68.52 13.92 70.35 1.34 M6 70.85 0.2069 0.33 0.03 0.2044 69.38 9.98 70.76 1.00 M7 70.93 0.2050 0.34 0.03 0.2005 68.20 19.46 70.72 1.81 M8 70.77 0.2047 0.36 0.05 0.2000 67.97 20.23 70.57 1.87

5. DISCUSSION Two main factors are related to the accuracy of this modeling approach. One is the accuracy of the current estimation method, and the other is the accuracy of the formulation of Ids as a function of L and W.

In our current estimation method, the estimated current is mainly determined by Islicing and slightly adjusted by Ioffset. It has been shown in [5] that the gate slicing method approximates the current well when the direction of the current flow is parallel to the L direction, which is the vertical direction in Figure 6(a). If the distortion of the gate contour is severe, this condition could be invalidated requiring a more accurate current estimation method. The offset current, Ioffset, is also an important factor to be characterized and modeled for each process. In Figure 9, we plotted (INRG - Islicing) and Ioffset for devices G1, G2, and G3 from Table 2. When estimating their currents, Ioffset is the same for these three cases since they have the same gate length at the edge. We can see that the offset currents of actual devices, (INRG - Islicing), are affected by the shape of the gate contour at the device edge. The ratio of (INRG - Islicing) to Islicing is about 0.3~0.4 to 1 for Ioff and 0.05~0.06 to 1 for Ion. In our experiments, the accuracy of our rough modeling of Ioffset is acceptable. However, in future devices, a good characterization of this offset current component would become necessary to accurately estimate device current, especially Ioff.

Figure 9. (INRG - Islicing) and Ioffset versus Vgs for device G1, G2 and G3.

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The quality of the formulation of Ids as a function of rectangular device L and W is another factor affecting the accuracy of this model. In other words, the correlation between the formulated Ids(L,W) should be as close to real Ids(L,W) as possible. A good formulation of Ids(L,W) ensures that less error is introduced in the process of modeling rectangular equivalent device from Iest. Therefore, the current of the equivalent device would be closer to that of the NRG device. As shown in Table 4, our model predicts Ion within about 0.05% and Ioff within 0.36% for the devices used in these experiments. Since in these experiments we assumed Iest is equal to INRG, the errors we observed came from the discrepancies between the formulated Ids(L,W) and Ids(L,W) of actual devices. In future devices, the correlation between Ids and W might deviate from a simple linear correlation. If that is the case, a higher order function will need to be used to express the function Ids(L,W).

In our TCAD experiments, both these two error components are observed. In our SPICE experiments, only the second error component is present.

6. CONCLUSIONS In this work we present a modeling approach for deriving an equivalent rectangular device from an NRG device. In contrast to the earlier works which compute only the equivalent gate length, we make the equivalent gate width an additional adjustable modeling parameter. By allowing both equivalent gate length and width adjustable during the modeling process, a single equivalent device can be obtained. The equivalent device derived from our modeling approach is validated on both TCAD and SPICE simulation platforms to capture accurately the on and off currents of the NRG device. The proposed modeling flow is very easy to implement and is inexpensive computationally.

ACKNOWLEDGMENTS

The first and third authors would like to gratefully acknowledge the support by SRC and by Mentor Graphics Corporation.

REFERENCES

[1] Poppe, W. J., Capodieci, L., Wu, J., and Neureuther, A., “From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistor,” Proc. SPIE 6156, 235-243 (2006).

[2] Gupta, P., Kahng, A., Kim, Y., Shah, S., and Sylvester, D., “Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis,” Proc. SPIE 6156, 285-294 (2006).

[3] Shi, S. X., Yu, P., and Pan, D., “A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power,” Proc. ICCAD, 423-428 (2006).

[4] Singhal, R., Balijepalli, A., Subramaniam, A.,Liu, F., Nassif, S., and Cao, Y., “Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation,” Proc. DAC, 823-828 (2007).

[5] Sponton, L., Bonholt, L., Pramanik, D., and Fichtner, W., “A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology,” Conference on Simulation of Semiconductor Process and Devices, 377-380 (2006).

[6] Oishi, T., Shiozawa, K., Furukawa, A., Abe, Y., and Tokuda, Y., “Isolation Edge Effect Depending on Gate Length of MOSFET’s with Various Isolation Structures” IEEE Trans. on Electron Devices, Vol. 47, No. 4, April, 822-827 (2006).

[7] Synopsys Sentaurus Manual, version Z_2007.03-SP1. [8] Sentaurus Technology Template: Process Emulation of 3D NMOS, http://solvnet.synopsys.com.

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