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© 2017 HRL Laboratories, LLC. All Rights Reserved
Low-Cost Gallium Nitride Vertical
Transistor
HRL: Yu Cao, Mary Chen, David Chow, Rongming Chu, Kangmu Lee, Ray Li
Virginia Tech: Dushan Boroyevich, Rolando Burgos, Christina DiMarino, Amy Romero
March 24, 2017
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© 2017 HRL Laboratories, LLC. All Rights Reserved
Project Objectives
1
• Objective: GaN vertical FET with 10X smaller power loss than Si IGBT
• Key Challenge: drift layer, gate structure, body contact, edge termination
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© 2017 HRL Laboratories, LLC. All Rights Reserved
Team
2
3-phase inverter
800V 30kW 40kHzGaN vertical diode & transistor switch
GaN EPI, Device fabrication, Characterization Power Circuits/Modules
• HRL plans to demonstrate a high-performance GaN vertical transistor in a
circuit developed by Virginia Tech.
• The team will identify and retire critical technical risks associated with epitaxial
material growth, device design/fabrication, and circuit demonstration.
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© 2017 HRL Laboratories, LLC. All Rights Reserved
GaN Trench MOSFET Process
3
3rd Year
Accomplishments
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© 2017 HRL Laboratories, LLC. All Rights Reserved
IV Characteristics
4
3rd Year
Accomplishments
28 μm
0 1 2 3 4 50
1
2
3
VGS
= 0 ~ +10 V, 2 V step
RON
=1.7
I D (
A)
VDS
(V)
0 2 4 6 8 1010
-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
I D, I G
(A
)
VGS
(V)
VDS
= 1 V
ID
IG
0 100 200 300 400 500 60010
-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
Id, Ig
(A
)
Vds (V)
Vgs=0V
Id
Ig
Li, Ray, et al. "600 V/$1.7~\ Omega $ Normally-Off GaN Vertical Trench
Metal–Oxide–Semiconductor Field-Effect Transistor." IEEE Electron
Device Letters 37.11 (2016): 1466-1469.
600-V-Class normally-off transistor demonstrated.
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© 2017 HRL Laboratories, LLC. All Rights Reserved
Temperature Dependent IV
5
0 2 4 6 8 100
1
2
3
4
5
6
I D (
A)
VDS
(V)
VGS
= 0, 1 , 2 , ... ,10 V
0 2 4 6 8 10100p
1n
10n
100n
1µ
10µ
100µ
1m
10m
100m
VDS
= 0.1 V
VGS
from 0 to 10V
22 oC
40 oC
70 oC
100 oC
125 oC
I D (
A)
VGS
(V)
100p
1n
10n
100n
1µ
10µ
100µ
1m
10m
100m
|IG| (A
)
20 40 60 80 100 120 1400
1
2
3
4
5
6
VDS
= 0.1 V
Up Sweep
Down Sweep
VT
H (
V)
Temperature (oC)
0 100 200 300 400 500 600100p
1n
10n
100n
1µ
10µ
100µ
1m
100 oC
70 oC
40 oCI D
, |I
G| (A
)
VDS
(V)
VGS
= 0 V
ID
|IG|
22 oC
20 40 60 80 100 120 1400.0
0.5
1.0
1.5
2.0
2.5
3.0
VGS
= 10V
VDS
= 0.1 V
VDS
= 1 V
RO
N (
ohm
)
Temperature (oC)
3rd Year
Accomplishments
• High on/off ration up to 125C.
• Positive temperature coefficient of Vth.
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© 2017 HRL Laboratories, LLC. All Rights Reserved
Switching Characteristics
6
3rd Year
Accomplishments
Test Parameters
VDD 400 V
VGS 0 V to 8 V
ID up to 2 A
Rg 2.5, 5, 10 Ω
RShunt 100 mΩ
Turn on voltage slew rate: ~100V/ns
Next steps:
• Reduce pitch size
• Optimize drift layer mobility
• Demonstrate 800V/10A Switching
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© 2017 HRL Laboratories, LLC. All Rights Reserved
Future Work
7
Project End Goals
1. Pitch Size• Reduce from 28um to 14um
2. Base Layer• Optimize thickness & doping
3. Drift Layer• Increase thickness from 8um to 16um
• Improve mobility to 1000 cm2/V-sec
4. Gate Trench• Accurate control of etch depth
• Round trench corner
5. Edge Termination
1. Pitch Size
2. Base Layer
3. Drift Layer
4. Gate Trench
5. E
dg
e T
erm
ina
tio
n
• HRL End of 2016 Measured: 1 mm2 chip, 800V/2A, 8~10 mohm-cm2, 400V/2A switching
• HRL End of 2017 Target: 1 mm2 chip, 1200V/10A, 2 mohm-cm2, 800V/10A switching
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© 2017 HRL Laboratories, LLC. All Rights Reserved
Technology-to-Market
8
Technology-to-
Market
• Objective: mature the technology to TRL(through ARPA-E SWITCHES), then to
TRL7, then transition to manufacturing partners
• Target Market Segments: open to all market segments, pathway to automotive and
aerospace market is important
• Value Proposition: >2X better performance over SiC, at lower cost
• Supply Chain Challenge: flat, uniform, defect-free, and large GaN substrates
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© 2017 HRL Laboratories, LLC. All Rights Reserved
Conclusions
9
• Demonstrated 600-V-class normally-off GaN vertical transistor
• Demonstrated fast switching at 400V/2AGaN
• Next step is to scale to 1200V/10A and demonstrate switching performance.