EE141 1 EE141 1 EECS141 EE141 EE141- Spring 2006 Spring 2006 Digital Integrated Digital Integrated Circuits Circuits Lecture 16 Lecture 16 SRAM Design SRAM Design EE141 2 EECS141 Announcements Announcements Project launch today Phase 1 due March 20 Homework #7 due next Thursday No new homework next week
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EE141EE141--Spring 2006Spring 2006Digital Integrated Digital Integrated CircuitsCircuits
Lecture 16Lecture 16SRAM DesignSRAM Design
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AnnouncementsAnnouncements
Project launch todayPhase 1 due March 20
Homework #7 due next ThursdayNo new homework next week
Last lectureDesign for speedMethod of logical effort
Today’s lectureSRAM design
Reading (Chapter 12)
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Logical Logical EffortEffort
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Optimum Effort per StageOptimum Effort per Stage
HhN =
When each stage bears the same effort:
N Hh =
( ) PNHpfgD Niii +=+= ∑ /1ˆ
Minimum path delay
Effective fanout of each stage: ii ghf =
Stage efforts: g1f1 = g2f2 = … = gNfN
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Optimal Number of StagesOptimal Number of StagesFor a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing
∑+= iN pNHD /1
NHh ˆ/1=The ‘best stage effort’
Remember: we can always add inverters to the end of the chain
Method of Logical EffortMethod of Logical EffortCompute the path effort: H = GBFFind the best number of stages N ~ log4HCompute the stage effort h = H1/N
Sketch the path with this number of stagesWork either from either end, find sizes: Cin = Cout*g/h