EE141 1 EECS141-S05 EE141 EE141- Spring 2005 Spring 2005 Digital Integrated Digital Integrated Circuits Circuits Lecture 10 Lecture 10 Introduction to wires Introduction to wires EECS141-S05 Administrative Stuff Administrative Stuff No Lab this week Midterm 1? Project first part to be announced next Tu
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EE141-Spring 2005 Digital Integrated Circuitsbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s05/...Vin Rs V out (r w,c ,L) EE141 36 EECS141-S05 Design Rules of Thumb rc delays should
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EE141
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EE141EE141--Spring 2005Spring 2005Digital Integrated Digital Integrated CircuitsCircuits
Lecture 10Lecture 10
Introduction to wiresIntroduction to wires
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Administrative StuffAdministrative Stuff
No Lab this weekMidterm 1?Project first part to be announced next Tu
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Last LectureLast Lecture
Last lectureCMOS scaling
Today’s lectureIntroduction to wires
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WiresWires
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The WireThe Wire
transmitte rs rece ivers
schematics physical
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Interconnect Impact on ChipInterconnect Impact on Chip
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Wire ModelsWire Models
All-inclusive model Capacitance-only
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Impact of Interconnect Impact of Interconnect ParasiticsParasiticsInterconnect parasitics
reduce reliabilityaffect performance and power consumption
Classes of parasiticsCapacitiveResistiveInductive
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10 100 1,000 10,000 100,000Length (u)
No
of n
ets
(Log
Sca
le)
Pentium Pro (R)Pentium(R) IIPentium (MMX)Pentium (R)Pentium (R) II
Nature of InterconnectNature of Interconnect
Local Interconnect
Global Interconnect
SLocal = STechnologySGlobal = SDie
Sour
ce: I
ntel
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INTERCONNECTINTERCONNECT
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Capacitance of Wire InterconnectCapacitance of Wire Interconnect
VDD VDD
VinVout
M1
M2
M3
M4Cdb2
Cdb1
Cgd12
Cw
Cg4
Cg3
Vout2
Fanout
Interconnect
VoutVin
CLSimplified
Model
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Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model
Die le ctric
Su bs trate
L
W
H
td i
Ele ctrica l-fie ld lines
Cu rre nt flow
WLt
cdi
diint
ε=
LLCwire SSS
SS 1=
⋅=
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PermittivityPermittivity
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Fringing CapacitanceFringing Capacitance
W - H/2H
+
(a)
(b)
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Fringing versus Parallel PlateFringing versus Parallel Plate
(from [Bakoglu89])
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InterwireInterwire CapacitanceCapacitance
fringing pa rallel
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Impact of Impact of InterwireInterwire CapacitanceCapacitance
More Interconnect Layersreduce average wire-length
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PolycidePolycide Gate MOSFETGate MOSFET
n+n+
SiO2
PolySilicon
Silicide
p
Silicides: WSi 2, TiSi2, PtSi2 and TaSi
Conductivity: 8-10 times better than Poly
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Sheet ResistanceSheet Resistance
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Modern InterconnectModern Interconnect
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Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process
5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric
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InterconnectInterconnect
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The Lumped ModelThe Lumped ModelVo ut
Drivercwire
VinClumped
Rdriver Vout
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The Distributed RC LineThe Distributed RC Line
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The Elmore DelayThe Elmore DelayRC ChainRC Chain
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Wire ModelWire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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StepStep--response of RC wire as a response of RC wire as a function of time and spacefunction of time and space
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge (
V)
x= L/10
x = L/4
x = L/2
x= L
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RC ModelsRC Models
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The Lumped RCThe Lumped RC--ModelModelThe Elmore DelayThe Elmore Delay
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Driving an RCDriving an RC--lineline
Vin
Rs Vout(rw,cw,L)
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Design Rules of ThumbDesign Rules of Thumbrc delays should only be considered when tpRC >> tpgate of the driving gate
Lcrit >> √ tpgate/0.38rcrc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line
trise < RCwhen not met, the change in the signal is slower than the propagation delay of the wire
Common Wire CrossCommon Wire Cross--SectionsSections
CoaxialCable
TriplateStrip Line
MicroStrip Wire aboveGround Plane
cl = εµ1
2
1
2
log2
log2
rr
rr
l
c
πµ
πε
=
=
c - capacitance/lengthl - inductance/length
=
=
Whl
Wh
c
µ
ε
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Inductance of package pinsInductance of package pins
Chip
MountingCavity
Lead Frame
Bonding Wire
Pin
L
L’
Make Rise- and Fall Times as slow as possible
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The Transmission LineThe Transmission Line
Vin
r l
c
r l
c
r l
c
r l
c
Voutx
g g g g
The Wave Equation
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Lossless Transmission Line Lossless Transmission Line -- ParametersParameters
vacuumspeed of light in
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Wave Propagation SpeedWave Propagation Speed
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Wave Reflection for Different TerminationsWave Reflection for Different Terminations
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Transmission Line Response (RTransmission Line Response (RLL== ∞∞))
0.0
1.0
2.0
3.0
4.0
5.0
V
0.0
1.0
2.0
3.0
4.0
V
0.0 5.0 10.0 15.0t (in tlightf)0.0
2.0
4.0
6.0
8.0
V
RS = 5Z0
RS = Z0
RS = Z0/5
(a)
(b)
(c)
VDestVSource
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Lattice DiagramLattice Diagram
VSource VDest
0.8333 V
1.6666 V+ 0.8333
+ 0.8333
+ 0.5556
+ 0.5556
+ 0.3704
+ 0.2469
+ 0.3704
+ 0.2469
2.2222 V
3.1482 V
3.7655 V
...
2.7778 V
3.5186 V
4.0124 V
L/ν
t
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Critical Line Lengths versus Rise TimesCritical Line Lengths versus Rise Times
(1990, Bakoglu)
100-200ps today
Lcrit ~ 1cm
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Design Rules of ThumbDesign Rules of ThumbTransmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight).
tr (tf) << 2.5 tflightTransmission line effects should only be considered when the total resistance of the wire is limited:
R < 5 Z0
The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance,
R < Z0/2
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Should we be worried?Should we be worried?
Transmission line effects cause overshooting and non-monotonic behavior
Clock signals in 400 MHz IBM Microprocessor(measured using e-beam prober) [Restle98]