EE141 1 EECS141 1 Lecture #20 EE141 EE141- Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 20 Lecture 20 Adders Adders EE141 2 EECS141 2 Lecture #20 Announcements Announcements Midterm 2: Thurs. Nov. 4 th , 6:30-8:00pm Exam starts at 6:30pm sharp Review session: Wed., Nov. 3 rd , 6pm Project phase 2 out this Thurs., due next Fri. Elad out of the office this afternoon Chintan will hold office hours today from 2-3pm Hanh-Phuc will hold extra office today from 4- 5pm Elad will hold extra office hours Thurs. 1-2pm EE141 3 EECS141 3 Lecture #20 Class Material Class Material Last lecture Dynamic logic Today’s lecture Adders Reading Chapter 11 EE141 4 EECS141 4 Lecture #20 Adders Adders EE141 5 EECS141 5 Lecture #20 An Intel Microprocessor An Intel Microprocessor 9-1 Mux 9-1 Mux 5-1 Mux 2-1 Mux ck1 CARRYGEN SUMGEN + LU 1000um b s0 s1 g64 sum sumb LU : Logical Unit SUMSEL a to Cache node1 REG Itanium has 6 64-bit integer execution units like this EE141 6 EECS141 6 Lecture #20 Bit Bit- Sliced Design Sliced Design Bit 3 Bit 2 Bit 1 Bit 0 Register Adder Shifter Multiplexer Control Data-In Data-Out Tile identical processing elements
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EE1411
EECS141 1Lecture #20
EE141EE141--Fall 2010Fall 2010Digital Integrated Digital Integrated CircuitsCircuits
Exam starts at 6:30pm sharpReview session: Wed., Nov. 3rd, 6pm
Project phase 2 out this Thurs., due next Fri.
Elad out of the office this afternoonChintan will hold office hours today from 2-3pmHanh-Phuc will hold extra office today from 4-5pmElad will hold extra office hours Thurs. 1-2pm
EE1413
EECS141 3Lecture #20
Class MaterialClass Material
Last lectureDynamic logic
Today’s lectureAdders
ReadingChapter 11
EE1414
EECS141 4Lecture #20
AddersAdders
EE1415
EECS141 5Lecture #20
An Intel MicroprocessorAn Intel Microprocessor
9-1
Mux
9-1
Mux
5-1
Mux
2-1
Mux
ck1
CARRYGEN
SUMGEN+ LU
1000um
b
s0
s1
g64
sum sumb
LU : LogicalUnit
SUM
SEL
a
to Cachenode1
REG
Itanium has 6 64-bit integer execution units like this
EE1416
EECS141 6Lecture #20
BitBit--Sliced DesignSliced Design
Bit 3
Bit 2
Bit 1
Bit 0
Reg
ister
Add
er
Shift
er
Mul
tiple
xer
Control
Dat
a-In
Dat
a-O
ut
Tile identical processing elements
EE1417
EECS141 7Lecture #20
Itanium Integer Itanium Integer DatapathDatapath
Fetzer, Orton, ISSCC’02
EE1418
EECS141 8Lecture #20
Data Paths Are Thermal HogsData Paths Are Thermal Hogs
EE1419
EECS141 9Lecture #20
FullFull--AdderAdderA B
Cout
Sum
Cin Fulladder
killkill
EE14110
EECS141 10Lecture #20
The Binary AdderThe Binary Adder
S A B Ci⊕ ⊕=
A= BCi ABCi ABCi ABCi+ + +
Co AB BCi ACi+ +=
EE14111
EECS141 11Lecture #20
Express Sum and Carry as a function of P, G, KExpress Sum and Carry as a function of P, G, K
Define 3 new variables which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A ⊕ BKill = A B
Can also derive expressions for S and Co based on K and P
Propagate (P) = A + BNote that we will sometimes use an alternate definition for
Goal: Make the fastest possible carry path circuit
FA FA FA FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
A3 B3
S3
Ci,0 Co,0
(= Ci,1)
Co,1 Co,2 Co,3
td = O(N)
tadder = (N-1)tcarry + tsum
EE14113
EECS141 13Lecture #20
Complementary Static CMOS Full Adder: Complementary Static CMOS Full Adder: ““DirectDirect”” ImplementationImplementation
28 Transistors
A B
B
A
Ci
Ci A
X
VDD
VDD
A B
Ci BA
B VDD
A
B
Ci
Ci
A
B
A CiB
Co
VDD
S
EE14114
EECS141 14Lecture #20
Complementary Static CMOS Full AdderComplementary Static CMOS Full Adder
28 Transistors
EE14115
EECS141 15Lecture #20
Inversion PropertyInversion Property
A B
S
CoCi FA
A B
S
CoCi FA
EE14116
EECS141 16Lecture #20
Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting Stages
Exploit Inversion Property
A3
FA FA FA
Even cell Odd cell
FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
B3
S3
Ci,0 Co,0 Co,1 Co,3Co,2
EE14117
EECS141 17Lecture #20
A Better Structure: The Mirror AdderA Better Structure: The Mirror Adder
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors
EE14118
EECS141 18Lecture #20
Sizing the Mirror Adder: Sizing the Mirror Adder: FanoutFanout• Since LE of carry gate is 2, want f of 2to get EF of 4
• Use min. size sum gates to reduceload on carry.
• Total load on carry gate is:
Cload = CCi + (6+6+9)Cload = 2CCi
EE14119
EECS141 19Lecture #20
Sizing the Mirror AdderSizing the Mirror Adder
• Cload = CCi + (6+6+9) = 2CCi
CCi = 21
• Minimum size G and K stacks to reduce diffusion loading
EE14120
EECS141 20Lecture #20
Mirror Adder SummaryMirror Adder Summary•The NMOS and PMOS chains are completely symmetrical. Maximum of two series transistors in the carry-generation gate.
•When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. Reduction of the diffusion capacitances is particularly important.
•Carry signals are critical - transistors connected to Ciare placed closest to the output.
•Only the transistors in the (propagate) carry chain have to be optimized for speed. All transistors in the sum stage can be minimal size.
EE14121
EECS141 21Lecture #20
Transmission Gate Full AdderTransmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
EE14122
EECS141 22Lecture #20
Manchester Carry ChainManchester Carry Chain
CoCi
Gi
Ki
Pi
Pi
VDD
EE14123
EECS141 23Lecture #20
Dynamic Manchester Carry ChainDynamic Manchester Carry Chain
CoCi
Gi
Ki
Pi
Pi
VDD
CoCi
Gi
Pi
VDD
φ
φ
EE14124
EECS141 24Lecture #20
Manchester Carry ChainManchester Carry Chain
G2
C3
G3Ci,0
P0
G1
VDD
G0
P1 P2 P3
C3C2C1C0
EE14125
EECS141 25Lecture #20
CarryCarry--Bypass AdderBypass Adder
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,3Co,2Co,1Co,0Ci,0
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,2Co,1Co,0Ci,0
Co,3
Mul
tiple
xer
BP=PoP1P2P3
Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.