EE141 – Fall 2005 Lecture 17 Dynamic Logic Dynamic Logic Adders Adders EE141 2 Announcements Project 1 due on Monday Oct 31 by 5pm • E-mail report to [email protected] • Don’t forget to attach SPICE deck Homework 7 will be posted today • Due next Thursday No labs next week
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1
EE141 – Fall 2005Lecture 17
Dynamic LogicDynamic LogicAddersAdders
EE141 2
Announcements
Project 1 due on Monday Oct 31 by 5pm• E-mail report to [email protected]• Don’t forget to attach SPICE deck
Homework 7 will be posted today• Due next Thursday
No labs next week
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Class Material
Last lecture• PTL
Today’s lecture• Dynamic Logic• Adders
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Alternative Logic Styles
Ratioed Logic• Reduced # of devices (reduced area)• Static power, reduced NML
DCVSL• Differential outputs, reduced # of devices• Doubles the # of wires, increased Pdynamic
Pass-Transistor Logic• Modular design (the same gate topology…)• Need level restoration
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Practical Guidelines
Ratioed Logic, DCVSL, PTL• Reduced # of devices (area)• Difficult to design• Poor noise robustness
Static CMOS• Larger area• Easy to design• Very robust
Use CMOS in designs with no extreme area, speed or complexity
constraints
Dynamic LogicDynamic Logic
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Dynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.• fan-in of n requires 2n devices
(n N-type + n P-type)
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.• Fan-in of n requires n + 2 transistors
(n+1 N-type + 1 P-type)
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Dynamic Gate: Basic Principle
In1
In2 PDNIn3
Me
Mp
CLK
CLKOut
CL
Out
CLK
CLK
A
BC
Mp
Me
Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)
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Dynamic Gate
In1
In2 PDNIn3
Me
Mp
CLK
CLKOut
CL
Out
CLK
CLK
A
BC
Mp
Me
Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)
on
off
1off
on
((AB)+C)
Out CLK A B C CLK= + ⋅ + ⋅
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Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next prechargeoperation.
Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
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Properties of Dynamic Gates
Logic function is implemented by the PDN only• # of transistors is N + 2 (vs. 2N in static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Nonratioed - sizing of the devices does not affect the logic levels
Faster switching speeds• reduced load capacitance due to lower input capacitance (Cin)• reduced load capacitance due to smaller output loading (Cout)• no Isc, so all the current provided by PDN goes into discharging CL
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Overall power dissipation usually higher than static CMOS• no static current path ever exists between VDD and GND
(including Psc)• no glitching• higher transition probabilities• extra load on CLK
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn• low noise margin (NML)
Needs a precharge/evaluate clock
Properties of Dynamic Gates
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Issues with Dynamic Gates
Charge Leakage
Charge Sharing
Capacitive Coupling
Clock Feedthrough
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CL
CLK
CLKOut
A
Mp
Me
Leakage sources
CLK
VOut
Precharge
Evaluate
Dynamic Design, Issue 1: Charge Leakage
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Solution to Charge Leakage
CL
CLK
CLK
Me
Mp
A
B
!Out
Mkp
Same approach as level restorer for pass transistor logic
Keeper
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CL
CLK
CLK
CA
CB
B=0
AOut
Mp
Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
Dynamic Design, Issue 2: Charge Sharing
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Charge Sharing Scenarios
Mp
Me
VDD
φOut
φ
A
B = 0
CL
Ca
Cb
Ma
Mb
X
CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=
or
∆Vout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =
∆Vout VDDCa
Ca CL+----------------------
–=
case 1) if ∆Vout < VTn
case 2) if ∆Vout > VTn
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Charge Sharing Example
CL=50fF
CLK
CLK
A !A
B !B B !B
C!C
Out
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
Worst-casecharge sharing:
!A*B*CA*!B*C
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Solution to Charge Redistribution
CLK
CLK
Me
Mp
A
B
OutMkp CLK
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
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Dynamic Design, Issue 3: Capacitive Coupling
CL1
CLK
CLK
B=0
A=0
Out1Mp
Me
Out2
CL2In
Dynamic NAND Static NAND
=1 =1
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Capacitive Coupling Effect
-1
0
1
2
3
0 2 4 6
Vol
tage
(V)
Time (ns)
CLK
In
Out1
Out2
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Dynamic Design, Issue 4: Clock Feedthrough
CL
CLK
CLK
B
AOut
Mp
Me
Coupling between Out and CLK input of the prechargedevice due to the gate to drain capacitance…
So voltage of Out can rise above VDD.
The fast rising (and falling edges) of the clock couple to Out.
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CLK
CLK
In1
In2
In3
In4
Out
In &CLK
Out
Time (ns)
Vol
tage
(V)
Clock feedthrough
Clock feedthrough
Clock Feedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
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Other Effects
Capacitive coupling (cross-talk)
Substrate coupling
Minority charge injection
Supply noise (ground bounce)
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Cascading Dynamic Gates
CLK
CLK
Out1In
Mp
Me
Mp
Me
CLK
CLK
Out2
V
t
CLK
In
Out1
Out2 ∆V
VTn
Only 0 → 1 transitions allowed at inputs!
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Cascading Dynamic Gates
Domino Logic
np-CMOS
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Domino Logic
In1
In2 PDNIn3
Me
Mp
CLK
CLK Out1
In4 PDNIn5
Me
Mp
CLK
CLKOut2
Mkp
1 → 00 → 0
1 → 1
0 → 1
Evaluation (conditional discharge)
ONLY 0→1 transitions during evaluation!
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Why Domino?
In1
CLK
CLK
Ini PDNInj
IniInj
PDN Ini PDNInj
Ini PDNInj
Like falling dominos!
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Properties of Domino Logic
Only non-inverting logic can be implemented
Very high speed• static inverter can be skewed, only L-H transition• Input capacitance reduced – smaller logical effort
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Designing with Domino Logic
Mp
Me
VDD
PDN
φ
In1In2
In3
Out1
φ
Mp
Me
VDD
PDN
φ
In4
φ
Out2
Mr
VDD
Inputs = 0during precharge
Can be eliminated!
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Footless Domino
Mp
VDD
CLK
Out1
In2 In1 1- >0 1->0
0->1
Mp
VDD
CLK
Out20- >1
In3 1->0
Mp
VDD
CLK
Outn
Inn 1->0
0->1
The first gate in the chain needs a foot switchPrecharge is rippling (next stage has to wait for propagation delay of inverter from the previous stage)
Static power consumption
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Differential (Dual Rail) Domino
A
B
Me
Mp
CLK
CLK!Out = !(AB)
!A !B
Mkp CLKOut = AB
Mkp Mp
Solves the problem of non-inverting logic
1 0 1 0
onoff
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np-CMOS
In1
In2 PDNIn3
Me
Mp
CLK
CLK Out1
In4 PUNIn5
Me
Mp!CLK
!CLK
Out2(to PDN)
1 → 11 → 0
0 → 00 → 1
Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN
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NORA Logic
In1
In2 PDNIn3
Me
Mp
CLK
CLK Out1
In4 PUNIn5
Me
Mp!CLK
!CLK
Out2(to PDN)
1 → 11 → 0
0 → 00 → 1
to otherPDN’s
to otherPUN’s
WARNING: Very sensitive to noise!P-blocks are slower
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Choosing a Logic Style: No Style Fits all Needs
General design Considerations• Robustness (Static CMOS, Ratioed Logic)• Area (Pseudo-NMOS, Static CMOS)• Speed (Dynamic, Ratioed Logic)• Power (Static CMOS, Dynamic Logic)
Application-specific considerations• XOR-dominated functions (PTL)
Design tool considerations• Static CMOS
AddersAdders
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A B
Cout
Sum
Cin Fulladder
Full Adder
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S A B Ci⊕ ⊕=
A= BCi ABCi ABCi ABCi+ + +
Co AB BCi ACi+ +=
A B
Cout
Sum
Cin Fulladder
The Binary Adder
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Define 3 new variables which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A ⊕ BDelete = A B
Can also derive expressions for S and Co based on D and P
Propagate (P) = A + BNote that we will be sometimes using an alternate definition for
Express Sum and Carry as a Function of P, G, D
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Worst case delay linear with the number of bits
Goal: Make the fastest possible carry path circuit
FA FA FA FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
A3 B3
S3
Ci,0 Co,0
(= Ci,1)
Co,1 Co,2 Co,3
td = O(N)
tadder = (N-1)tcarry + tsum
The Ripple-Carry Adder
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28 Transistors
A B
B
A
Ci
Ci A
X
VDD
VDD
A B
Ci BA
B VDD
A
B
Ci
Ci
A
B
A CiB
Co
VDD
S
Complimentary Static CMOS Full Adder
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A B
S
CoCi FA
A B
S
CoCi FA
Inversion Property
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Exploit Inversion Property
A3
FA FA FA
Even cell Odd cell
FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
B3
S3
Ci,0 Co,0 Co,1 Co,3Co,2
Minimize Critical Path by Reducing Inverting Stages
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VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
A Better Structure: The Mirror Adder
24 Transistors
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Mirror Adder
Stick Diagram
CiA B
VDD
GND
B
Co
A Ci Co Ci A B
S
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The Mirror AdderThe NMOS and PMOS chains are completely symmetrical.A maximum of two series transistors can be observed in the carry-generation circuitry.When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell.The transistors connected to Ci are placed closest to the output.Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.
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A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Transmission Gate Full Adder
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Manchester Carry Chain
CoCi
Gi
Di
Pi
Pi
VDD
CoCi
Gi
Pi
VDD
φ
φ
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Manchester Carry Chain
G2
φ
C3
G3Ci,0
P0
G1
VDD
φ
G0
P1 P2 P3
C3C2C1C0
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Ci,0 G0
CLK
CLKP0 P1 P2 P3
G1 G2 G3
Ci,41234
5
6
3 3 3 3 3
1
2
2
3
3
4
4
5
!(G0 + P0 Ci,0) !(G1 + P1G0 + P1P0 Ci,0)
Domino Manchester Carry Chain
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Manchester Carry Chain
Pi + 1 Gi + 1 φ
Ci
Inverter/Sum Row
Propagate/Generate Row
Pi Gi φ
Ci - 1Ci + 1
VDD
GND
Stick Diagram
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FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,3Co,2Co,1Co,0Ci,0
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,2Co,1Co,0Ci,0
Co,3
Mul
tiple
xer
BP=PoP1P2P3
Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.
Also called Carry-Skip
Carry-Bypass Adder
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Carrypropagation
SetupBit 0–3
Sum
M bits
tsetup
tsum
Carrypropagation
SetupBit 4–7
Sum
tbypass
Carrypropagation
SetupBit 8–11
Sum
Carrypropagation
SetupBit 12–15
Sum
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum
Carry-Bypass Adder (Cont.)
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Carry Ripple vs. Carry Bypass
tp
N4-8
Ripple adder
Bypass adder
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Next Lecture
Carry-Select AddersLook-Ahead Adders
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