EE141 1 EE141 EECS141 1 Lecture #18 EE141-Fall 2012 Digital Integrated Circuits Lecture 18 Ratioed and Pass Transistor Logic EE141 EECS141 2 Lecture #18 Announcements Project #1 due Thursday EE141 EECS141 3 Lecture #18 Ratioed Logic EE141 EECS141 4 Lecture #18 Ratioed Logic V DD V SS PDN In 1 In2 In 3 F R L Load V DD V SS In 1 In2 In 3 F V DD V SS PDN In 1 In2 In 3 F VSS PDN Resistive Depletion Load PMOS Load (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS VT < 0 Goal: build gates faster/smaller than static complementary CMOS EE141 EECS141 5 Lecture #18 Ratioed Logic Spend power for speed Use pseudo nMOS NOR gates, not NAND gates DC characteristics: V OH = V DD V OL depends on PMOS to NMOS ratio W W W W EE141 EECS141 6 Lecture #18 Pseudo-NMOS VTC 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V in [V] V out [V] W/Lp = 4 W/L p = 2 W/L p = 1 W/Lp = 0.25 W/L p = 0.5
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EE141-Fall 2012 Ratioed Logic Digital Integratedbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f12/... · 2012-10-19 · EE141 1 EECS141EE141 Lecture #18 1 EE141-Fall 2012 Digital
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