EE141 1 EE141 EECS141 1 Lecture #17 EE141-Fall 2012 Digital Integrated Circuits Lecture 17 CMOS Scaling EE141 EECS141 2 Lecture #17 Announcements Homework #7 due today Project #1 out today, due next Thurs. Midterm 2 two weeks from today Let us know ASAP if you still don’t have a project partner
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EE141-Fall 2012 Digital Integrated Circuitsbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f12/... · 2012. 10. 19. · EE141 1 EECS141EE141 Lecture #17 1 EE141-Fall 2012 Digital Integrated
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EE141
1
EE141EECS141 1Lecture #17
EE141-Fall 2012Digital Integrated Circuits
Lecture 17CMOS Scaling
EE141EECS141 2Lecture #17
Announcements
Homework #7 due today Project #1 out today, due next Thurs.
Midterm 2 two weeks from today
Let us know ASAP if you still don’t have a project partner
EE141
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EE141EECS141 3Lecture #17
CMOS Transistor Scaling
EE141EECS141 4Lecture #17
Goals of Technology Scaling
Make things cheaper: Want to sell more functions (transistors)
per chip for the same money
Or build same products cheaper
Price of a transistor has to be reduced
But also want to be faster, smaller, lower power…
EE141
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EE141EECS141 5Lecture #17
Technology Scaling
Benefits of 30% “Dennard” scaling (1974): Double transistor density
Reduce gate delay by 30% (increase operating frequency by 43%)
Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency)
Die size used to increase by 14% per generation (not any more)
Technology generation spans 2-3 years
EE141EECS141 6Lecture #17
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
• Fixed Voltage Scaling
• General Scaling
ideal model — dimensions and voltages scaletogether by the same factor S
most common model until 1990’sonly dimensions scale, voltages remain constant
most realistic for today’s situation —voltages and dimensions scale with different factors
EE141
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EE141EECS141 7Lecture #17
ScalingL
x
LD
L/S
x/S
LD/S
L
W
L/S
W/S
EE141EECS141 8Lecture #17
Full Scaling (Dennard, Long-Channel)
W, L, tox: 1/S
VDD, VT: 1/S
Area: WL
Cox: 1/tox
CL: CoxWL
ID: Cox(W/L)(VDD-VT)2
Req: VDD/IDSAT
EE141
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EE141EECS141 9Lecture #17
Full Scaling (Dennard, Long-Channel)
W, L, tox: 1/S
VDD, VT: 1/S
tp: ReqCL
Pavg: CLVDD2/tp
Pavg/A: CoxVDD2/tp
EE141EECS141 10Lecture #17
Scaling Relationships for Long Channel Devices
EE141
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EE141EECS141 11Lecture #17
Full Scaling (Dennard, Short-Channel)
W, L, tox: 1/S
VDD, VT: 1/S
Area: WL
Cox: 1/tox
CL: CoxWL
ID: WCoxvsat(VDD-VT)2/(VDD-VT-EcritL)
Req: VDD/IDSAT
EE141EECS141 12Lecture #17
Full Scaling (Dennard, Short-Channel)
W, L, tox: 1/S
VDD, VT: 1/S
tp: ReqCL
Pavg: CLVDD2/tp
Pavg/A: CoxVDD2/tp
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EE141EECS141 13Lecture #17
Transistor Scaling(Velocity-Saturated Devices)
EE141EECS141 14Lecture #17
Interconnect Scaling
EE141
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EE141EECS141 15Lecture #17
Interconnect Length Distribution
From Magen et al., “Interconnect Power Dissipation in a Microprocessor”