EE141 – Fall 2005 Lecture 3

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EE141 – Fall 2005Lecture 3

CMOS ManufacturingCMOS ManufacturingDesign RulesDesign Rules

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Administrative Stuff

The course web-page is up• http://bwrc.eecs.berkeley.edu/Classes/ee141• http://inst.eecs.berkeley.edu/~ee141

Labs start next week• Everyone should have an EECS instructional account• http://www-inst.eecs.berkeley.edu/

~inst/newusers.html

Homework #1 is due this Thursday before class• Drop-off box 240 Cory

Homework #2 will post on Thursday, Sep-8

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TA Office Hours

TA office hours in 197 Cory• Lynn Wang, Tue 1:30-2:30pm• Ke Lu, Wed 2-3pm

Check the newsgroup for questions

Email Dejan and TAs: [email protected]

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Last Lecture

Last lecture• Design metrics

Today’s lecture• CMOS manufacturing process• CMOS design rules

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Review

Design MetricsDesign Metrics• Cost• Reliability• Speed• Power

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Total Cost

Cost per IC

Variable cost

volumecost fixed ICper cost variable ICper cost +=

yield test finalpackaging ofcost test die ofcost die ofcost cost variable ++

=

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Die Cost

Single die

Wafer

Going up to 12” (30cm)

yield die*per wafer dies waferofcost die ofcost =

From: http://www.amd.com

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Defects

α−

α×

+=area dieareaunit per defects1yield die

α ≈ 3, complexity of mfg. process

defects per unit area = 0.5 to 1 /cm2

cost of die = f (die area)4

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V(in)

V(out)

fV(out)=V(in)

Switching Threshold

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

DC Operation:Voltage Transfer Characteristic

VOH

VOL

VM

VOL VOH

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Slope = -1

Slope = -1

VOL

VIL

VIH

VOH

UndefinedRegion

Mapping between Analog and Digital Signals

“1”

“0”VOL

VOH

V(out)

V(in)VIL VIH

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UndefinedRegion

Noise margin high:NMH = VOH – VIH

Noise margin low:NML = VIL – VOL

Gate Output

Gate Input

Definition of Noise Margins

NML

NMH

“0”

“1”

VOL

VOH

VIL

VIH

(Stage M) (Stage M+1)

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Ri = ∞Ro = 0Fanout = ∞NMH = NML = VDD/2g = −∞

The Ideal Gate

V(in)

V(out)

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Outline


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Vout

tf

tpHL tpLH

trt

Vin

t

90%

10%

50%

50%2

pHLpLHp

ttt

+=

Performance: Delay Definitions

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v0 v1 v5

v1 v2v0 v3 v4 v5

T = 2 × tp × N

Technology Characterization:Ring Oscillator for tp

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Performance: FO4 Inverter

Measures quality of design across different technology generations

d

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A First-Order RC Network

vout

v in C

R

Important model – matches delay of inverter

int

out vetv ⋅−= − )1()( τ

Step response:

RCt p 69.02ln =⋅= τPropagation delay:

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Review


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Power Dissipation

( )∫ ∫+ +

⋅=⋅=Tt

t

Tt

t supplydd

avg dttiT

VdttpT

P )(1

peakddpeak iVP ⋅=

( )tiVtitvtp supplydd ⋅=⋅= )()()(Instantaneous power

Peak power

Average power

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Energy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pavg × tp

Energy-Delay Product (EDP) =

quality metric of gate = E × tp

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A First-Order RC Network

vout

vin CL

R

( )∫ ∫∫ ⋅=⋅=⋅=⋅=→

T V

ddLoutL

T

ddsupplydddd VCdVCVdttiVdttpE

0 0

2

010 )(

( ) ( )∫ ∫∫ ⋅⋅=⋅⋅=⋅⋅=⋅=T V

ddLoutoutL

T

capoutcapcapdd VCdVtVCdttitVdttpE

0 0

2

0 21)()(

1021

→= EEcap

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Outline

MOS TransistorMOS Transistor

Manufacturing ProcessManufacturing Process

Design Rules & LayoutDesign Rules & Layout

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The MOS Transistor

PolysiliconAluminum

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CMOS Process

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A Modern CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS Process

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Transistor Layout

p-well SiO2

poly

SiO2

n+

Cross-Sectional View

Layout View

poly

p-well

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Circuit Under Design

VDDVDD

VinVout

M1

M2

M3

M4Vout2

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Polysilicon

In Out

VDD

GND

PMOS 2λ

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

CMOS Inverter

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Two Inverters

Connect in Metal

VDD

Share power and ground

Abut cells

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Outline




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oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic Process

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Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-lightPatternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

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CMOS Process at a Glance

Define active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

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CMOS Process Walk-Through

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epi SiO2

3SiN

4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)

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SiO2(d) After trench filling, CMPplanarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

n

(f) After p-well andVTn adjust implants

p

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(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2

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(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.

AlSiO2

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Advanced Metalization

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Advanced Metalization

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Outline




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Design Rules

Interface between designer and process engineer

Guidelines for constructing process masks

Unit dimension: Minimum line width• Scalable design rules: lambda parameter• Absolute dimensions (micron rules)

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Design Rules

Intra-layer• Widths, spacing

Inter-layer• Enclosures, overlaps

Special rules (sub-0.25µm)• Area, antenna rules, density rules

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CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

RedBlue

MagentaBlack

BlackBlack

Select (p+,n+) Green

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Layers in 0.25µm CMOS Process

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Design Rules

Intra-layer: widths, spacing

Inter-layer: enclosures, overlaps• Transistor rules• Contact and via rules• Well and substrate contacts

Special rules (sub-0.25µm)• Area, antenna rules, density rules

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Intra-Layer Design Rules

Metal2 4

3

10

90

Well

Active3

3

Polysilicon2

2

Different PotentialSame Potential

Metal1 3

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Contactor Via

Select2

or6

2Hole

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1

2

5

3

Tran

sist

or

Inter Layer: Transistor Rules

Tran

sist

or

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Inter Layer: Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

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1

3 3

2

2

2

WellSubstrate

Select3

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Inter Layer: Well and Substrate

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Example: CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

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Layout Editor – MicroMagic

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Layout Editor –Cadence Virtuoso

In1 In2Out

vdd

gnd

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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities• Only topology is important

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Next Lecture

MOS Transistor• Operation and modeling

EE141 – Fall 2005 Lecture 3

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