ECAD LAB Department Of ECE
ECAD LAB Department Of ECE
ELECTRONIC COMPUTER AIDED DESIGN LABORATORYIII Year-II Semester
List of Experiments:1. Realization Of Logic Gates 2. 3 to 8 decoder
-741383. 8 x 1 Multiplexer -74151 and 2x4 De-Multiplexer-74155 4. 4
bit comparator -74855. D-Flipflop - 74746. Decade counter -74907.
4-bit counter -74938. Shift Register -74959. Universal shift
Register -7419510. RAM(16x4)-74189(Read and write operations)11.
Stack and Queue implementation using RAM12. ALU DesignAdd-on
Experiments:1. Half adder and Full Adder.
Gate Representation:
EXNOR
1. REALIZATION OF LOGIC GATESAim: To Design VHDL model for all
Logic Gates and verify the functionality and output waveforms using
Xilinx ISE Software.Apparatus:1. Personal Computer2. Xilinx ISE
Software. Procedure:1. Start Xilinx ISE by double clicking on ISE
Design suite 14.4 icon on the desktop.2. Create a new project by
selecting FileNew Project. The New Project Wizard appears.3. Give
the project name in the Project Name field and check whether the
location is in C:\.Xilinx path. Verify that HDL is selected from
the Top-Level Source Type list.4. Click Next to move to the device
properties page. Fill in the properties in the table Product
Category: All Family: Spartan3E Device: XC3S100E, Package:
VQ100,Speed Grade: -5 Top-Level Source Type: HDL Synthesis Tool:
XST (VHDL/Verilog) Simulator: Isim Simulator (VHDL/Verilog)
Preferred Language: VHDL5. Click Next then Finish.6. Create the
top-level Schematic source file for the project as follows: Project
New source New source wizard window will appear.7. Select VHDL
Module as the source type in the New Source dialog box. Give the
file name for the source file. Verify that the Add to Project
checkbox is selected. 8. Click Next. Then declare the ports for the
design by filling in the port information. Click Next, then
Finish.7. Enter the VHDL code and check for errors by
Double-clicking the Check Syntax.8. Verify that Behavioral
Simulation and design sources are selected in the Sources window.
Double-click the Simulate Behavioral Model observe the output
waveforms.
Truth Table:
Program:Data Flow Model:Library IEEE;Use
IEEE.STD_LOGIC_1164.ALL;Entity logic gates isPort(a,b: in
STD_LOGIC; c,d,e,f,g,h,i:out STD_LOGIC);end logic
gates;architecture behavioral of logic gates isbeginc