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    ECAD LAB

    AVANTHI’S

    St. THERESSA INSTITUTE

    OF ENGINEERING & TECHNOLOGY(Approved by A.I.C.T.E Reco!"#ed by t$e Govt. o% A. & A%%"'"ted to )NTU* +,"!d-

    GARIVII (C$ep/r/p''"-* V"#"!r0 "1t. (A.-

    EART2ENT OF ELECTRONICS AN CO22UNICATION

    ENGINEERING

     ELECTRONIC COMPUTER AIDED DESIGN LABORATORY 

     NAME : _________________________________________

    ROLL NO : _________________________________________ 

    BRANCH : _________________________________________ 

    ASTIET Page 1Dept. of ECE

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    ECAD LAB

    INE3

    S.No N0e o% T$e E4per"0e!t te Re0r,1

    (Lb I!5c$re-

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    ECAD LAB

    HAR6ARE

    E3ERI2ENTS

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    ECAD LAB

    7. LOGIC GATES

    AI28 To stu! a" #e$%f! t&e t$ut& ta'(es of Log%) *ates.

    AARATUS8 1.(og%) gates t$a%"e$ +%t

    2.IC ,-/0 IC ,-320 IC ,--0 IC ,-0 IC ,-20 IC ,-/0 IC,-2

    3. pat)& )a$s

    AN te (IC 9:;

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    ECAD LAB

    OR te (IC 9:>?- e%"!"t"o!8

    A Lo"c OR Gte o$ I")(us%#e;OR gate %s a t!pe of %g%ta( (og%) gate t&at &as a" output &%)&

    %s "o$a((! at (og%) (e#e( 44 a" o"(! goes 4HI*H4 to a (og%) (e#e( 414 &e" o"e o$ o$e of %ts

    %"puts a$e at (og%) (e#e( 414. T&e output0 of a Lo"c OR Gte o"(! $etu$"s 4LO54 aga%" &e" ALL

    of %ts %"puts a$e at a (og%) (e#e( 44. T&e (og%) o$ Boo(ea" e6p$ess%o" g%#e" fo$ a (og%) OR gate %s t&at

    fo$  Logical Addition  &%)& %s e"ote '! a p(us s%g"0 7 < 8 g%#%"g us t&e Boo(ea" e6p$ess%o"

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    ECAD LAB

    LOGIC SY2=OL8

    IN IAGRA28

    TRUTH TA=LE8

    NAN te (IC 9:;;- e%"!"t"o!8

    T&e Lo"c NAN Gte  %s a )o'%"at%o" of t&e %g%ta( (og%) AND gate %t& t&at of a"

    %"#e$te$ o$ NOT gate )o""e)te toget&e$ %" se$%es. T&e NAND 7Not ; AND8 gate &as a" output t&at %s

    "o$a((! at (og%) (e#e( 414 a" o"(! goes 4LO54 to (og%) (e#e( 44 &e" ALL of %ts %"puts a$e at

    (og%) (e#e( 414. T&e Lo"c NAN Gte %s t&e $e#e$se o$ 4Complementary4 fo$ of t&e AND gate e

    &a#e see" p$e#%ous(!.

    LOGIC SY2=OL8

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    ECAD LAB

    IN IAGRA28

    9:;;

    TRUTH TA=LE8

    NOR te (IC 9:;?- e%"!"t"o!8

    T&e Lo"c NOR Gte o$ I")(us%#e;NOR gate %s a )o'%"at%o" of t&e %g%ta( (og%) OR gate

    %t& t&at of a" %"#e$te$ o$ NOT gate )o""e)te toget&e$ %" se$%es. T&e NOR 7Not ; OR8 gate &as a"

    output t&at %s "o$a((! at (og%) (e#e( 414 a" o"(! goes 4LO54 to (og%) (e#e( 44 &e" ANY of %ts

    %"puts a$e at (og%) (e#e( 414. T&e Lo"c NOR Gte %s t&e $e#e$se o$ 4Complementary4 fo$ of t&e OR gate e &a#e see" p$e#%ous(!.

    LOGIC SY2=OL8

    IN IAGRA28

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    ECAD LAB

    TRUTH TA=LE8

    3OR te (IC 9:ua(0 t&e" t&e output %(( 'e ?@.

    LOGIC SY2=OL8

    IN IAGRA28

    TRUTH TA=LE8

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    ECAD LAB

    3NOR te (IC 9:?@@- e%"!"t"o!8

    T&e E4c'/1"ve5NOR Gte fu")t%o" o$ E6;NOR fo$ s&o$t0 %s a %g%ta( (og%) gate t&at %s t&e

    $e#e$se o$ )op(ee"ta$! fo$ of t&e E6)(us%#e;OR. T&e E6)(us%#e;NOR gate %s a )o'%"at%o" of 

    t&e E6)(us%#e;OR gate a" t&e NOT gate. It &as a" output t&at %s "o$a((! at (og%) (e#e( 44 &e"

    ANY of %ts %"puts a$e at (og%) (e#e( 414.

    LOGIC SY2=OL8

    IN IAGRA28

      IC 9:?@@

    TRUTH TA=LE8

    ROCEURE8

    1. Co""e)t t&e IC as s&o" %" f%gu$es fo$7AND0OR0NAND0NOR a" E6;OR gates8.

    2. App(! t&e (og%) s%g"a( o$ 1 f$o t&e (og%) %"put s%t)&es at %"put A B.

    3. Mo"%to$ t&e output us%"g (og%) output LED %"%)ato$.

    RESULT8

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    ECAD LAB

    ?. > TO < ECOER 9:7><

    AI28 To #e$%f! t&e ope$at%o" of t&e 3 to / e)oe$ 7,-13/8.

    AARATUS8 1. 3 to / e)oe$ t$a%"e$ +%t

    2. IC ,-13/3. pat)& )a$

    THEORY8

    A e)oe$ %s a u(t%p(e;%"put0 u(t%p(e output (og%) )%$)u%t t&at )o"#e$ts )oe %"puts %"to

    )oe outputs0 &e$e t&e %p"put a" output )oes a$e %ffe$e"t. T&e %"put )oe ge"e$a((! &as fee$ 

     '%ts t&a" t&e output )oe.

    IN IAGRA28

    FUNCTION TA=LE:

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    ECAD LAB

    LOGIC IAGRA2:

    ROCEURE

    1. Ma+e t&e )o""e)t%o"s as pe$ )%$)u%t %ag$a.

    2. C&a"ge t&e #a(ues of *10 *2A0 *3B0 A0 B0 C us%"g s%t)&es

    3. O'se$#e status of to , o" LEDs as fo$ t$ut& ta'(e.

    RESULT8

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    ECAD LAB

    >.< 4 7 2ULTILE3ER 9:77

    AI28 To stu! t&e ope$at%o" a" #e$%f%)at%o" of / 6 1 u(t%p(e6e$ 7,-1=18.

    AARATUS8 1. / 6 1 u(t%p(e6e$ t$a%"e$ +%t

    2. IC ,-1=1

    3. pat)& )a$s

    THEORY8

    T&e 1=1 se(e)ts o"e;of;e%g&t ata sou$)es. T&e 1=1A &a#e a st$o'e %"put &%)& ust 'e at a

    (o (og%) (e#e( to e"a'(e t&ese e#%)es. A &%g& (e#e( at t&e st$o'e fo$)es t&e 5 output &%g& a" t&e

    output 7as app(%)a'(e8 (o.

    ROCEURE8

    1. S%t)& o" t&e t$a%"e$2. Co""e)t ata %"put 7I;I,8 to (og%) s%t)&es %t& t&e &e(p of %$e )o""e)t output to (og%) %"%)ato$.

    3. Put S9o0 S19 a" o'se$#e t&e output '! )&a"g%"g %"put (ea#es. 5%t& t&%s e )a" "ot%)e t&at t&e

    output %s fo((o%"g o"(! Ia" t&e ot&e$ %"put )a""ot affe)t t&e output.

    -. O'se$#e u6 output fo$ S0 S10 a" S2 )o'%"at%o" a" #e$%f! $esu(t %t& t&e t$ut& ta'(e.

    e 0/4

    =. e$%f! t&e output '! us%"g se(e)t (%"es A &as a)t%#e &%g& %"put a" us%"g se(e)t (%"es B &as a" a)t%#e

    (o output.

    . Put a(a!s st$o'e %.e.*aF* ' %" (o.

    IN IAGRA28

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    ECAD LAB

    TRUTH TA=LE8

    LOGIC IAGRA28

    RESULT8

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    ECAD LAB

    :. :5="t CO2ARATOR 9:

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    ECAD LAB

    FUNCTION TA=LE8

    LOGIC IAGRA28

    ROCEURE

    1. Co""e)t t&e )%$)u%t ass&o" %" f%gu$e. ee t&e -;

     '%t '%"a$! o$ A0A10A20

    A3 a" B0B10B20B3 f$o

    (og%) %"put S%t)&es .

    2. P%" 3 of IC ,-/= s&ou(

     'e (og%) %"put 1 to e"a'(e

    )opa$ato$ ope$at%o".

    3. O'se$#e t&e output

    AB0A9B0 AGB o" (og%)

    %"%)ato$. T&e output ost

     'e 1 o$ $espe)t%#e(!

    -. Repeat t&e step 102 a" 3

    fo$ #a$%ous %"put

    A0A10A20A3 a"

    B0B10B20B3.

    RESULT8

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    ECAD LAB

    . FLI5FLO 9:9:

    AI28 To stu! t&e ope$at%o" of D (%p;(op 7,-,-8.

    AARATUS8 1. D (%p;(op t$a%"e$ +%t

    2. IC ,-,-

    3. pat)& )a$sTHEORY8

    T&ese e#%)e )o"ta%"sto %"epe"e"t D;t!pe pos%t%#e ege t$%gge$e f(%p;f(ops. A (o (e#e(

    at &e p$eset o$ )(ea$ %"puts set o$ $esets t&e output $ega$(ess of t&e (e#e(s of t&e ot&e$ %"puts. 5&e"

     p$eset a" )(ea$ a$e %"a)t%#e0 ata at t&e D f(%p;f(op %"puta$e t$a"sfe$$e to t&e output o" t&e pos%t%#e

    go%"g ege of t&e )(o)+ pu(se.

    ROCEURE8

    1. Co""e)t t&e (og%) gate of D;f(%p f(op as s&o" %" f%gu$e.

    2. App(! t&e (og%) s%g"a( o$ 1 f$o t&e (og%) %"put s%t)&es at t&e %"put A a" B.

    3. O'se$#e t&e output at LED %"%)ato$.

    IN IAGRA28

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    ECAD LAB

    FUNCTION TA=LE8

    LOGIC IAGRA28

    RESULT8

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    ECAD LAB

    @.ECAE COUNTER 9:B;

    AI28 To stu! t&e ope$at%o" of e)ae )ou"te$ 7,-8.

    AARATUS8 1. e)ae )ou"te$ t$a%"e$ +%t

    2. IC ,-

    3. pat)& )a$sTHEORY8

    Ea)& of t&ese o"o(%t&%) )ou"te$s )o"ta%"s fou$ aste$ s(a#e f(%p;f(ops a" a%t%o"a( gat%"g

    to p$o#%e a %#%e;'! to )ou"te$ a" a t&$ee;stage '%"a$! )ou"te$ fo$ &%)& t&e )ou"t )!)(e (e"gt& %s

    %#%e;'!;f%#e fo$ t&e DM,-LS. A(( of t&ese )ou"te$s &a#e a gate Je$o $eset a" t&e DM,-LS

    a(so &as gate set;to;"%"e %"puts fo$ use %" BCD "%"es )op(ee"t app(%)at%o"s. To use t&e%$ 

    a6%u )ou"t (e"gt& 7e)ae o$ fou$ '%t '%"a$!80 t&e B %"put %s )o""e)te to t&e A output. T&e

    %"put )ou"t pu(ses a$e app(%e to %"put A a" t&e outputs a$e as es)$%'e %" t&e app$op$%ate t$ut& ta'(e.

    A s!et$%)a( %#%e;'!;te" )ou"t )a" 'e o'ta%"e f$o t&e DM,-LS )ou"te$s '! )o""e)t%"g t&e

    D output to t&e A %"put a" app(!%"g t&e %"put )ou"t to t&e B %"put &%)& g%#es a %#%e;'!;te"

    s>ua$e a#e at output A.

    IN IAGRA28

    RESETCOUNT

    TRUTH TA=LE8

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    ECAD LAB

    LOGIC IAGRA28

    ROCEURE

    1. S%t)& Ko" t&e t$a%"e$.

    2. Ma+e t&e )o""e)t%o"s as pe$ )%$)u%t %ag$a.

    3. Co""e)t t&e %"put B to t&e a output.

    -. Put $eset at %"puts Ro10 Ro20 So10So2as g%#e" %" t&e )ou"t t$ut& ta'(e.

    =. App(! t&e pu(se f$o ; a" o'se$#e t&e outputs at a0'0)0 fo$ ea)& pu(se.

    RESULT8

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    ECAD LAB

    9. :5=IT =INARY COUNTER 9:B>

    AI28 To stu! t&e ope$at%o" of -;'%t '%"a$! )ou"te$ 7,-38.

    AARATUS8 1. -;'%t '%"a$! )ou"te$ t$a%"e$ +%t

    2. IC ,-3

    3. pat)& )a$sTHEORY8

    T&e )ou"te$ )o"ta%"s fou$ aste$ s(a#e f(%p;f(ops a" a%t%o"a( gat%"g to p$o#%e a %#%e;'!

    to )ou"te$ a" a t&$ee;stage '%"a$! )ou"te$ fo$ &%)& t&e )ou"t )!)(e (e"gt& %s %#%e;'!;e%g&t fo$ 

    t&e 3A. A(( of t&ese )ou"te$s &a#e a gate Je$o $eset.

    To use t&e%$ a6%u )ou"t (e"gt& 7e)ae o$ fou$;'%t '%"a$!80 t&e B %"put %s )o""e)te to

    t&e A output. T&e %"put )ou"t pu(ses a$e app(%e to %"put A a" t&e outputs a$e as es)$%'e %" t&e

    app$op$%ate t$ut& ta'(e. A s!et$%)a( %#%e;'!;te" )ou"t )a" 'e o'ta%"e f$o t&e A )ou"te$s '!

    )o""e)t%"g t&e D output to t&e A %"put a" app(!%"g t&e %"put )ou"t to t&e B %"put &%)& g%#es a

    %#%e;'!;te" s>ua$e a#e at output A.

    IN IAGRA28

    RESETCOUNT TRUTH TA=LE8

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    ECAD LAB

    LOGIC IAGRA28

    ROCEURE8

    1. S%t)& Ko" t&e t$a%"e$.2. Ma+e t&e )o""e)t%o"s as pe$ )%$)u%t %ag$a

    3. Put $eset at %"puts Ro10 Ro2&as g%#e" %" t&e )ou"t t$ut& ta'(e.

    -.App(! t&e pu(se f$o ;1= a" o'se$#e t&e outputs at a0'0)0 fo$ ea)& pu(se.

    RESULT8

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    ROCEURE

    1. S%t)& KON t&e t$a%"e$.

    2. Ma+e t&e )o""e)t%o"s as pe$ t&e )%$)u%t %ag$a.

    3. App(! (og%) K o" CLR p%"0 o'se$#e t&e output.

    -. Put S10 S0 CL0 CLR to (og%) 10 a" o'se$#e t&e output %s fo((o%"g t&e %"put.

    =. C&a"ge t&e S1 pos%t%o" to (o 7(og%) 80 put SRSI910 O'se$#e t&e outputs.

    . C&a"ge t&e SRSI to (og%) K aga%" o'se$#e t&e output

    ,. Repeat t&e step = fo$ +eep%"g SLSI to (og%) K aga%" o'se$#e t&e output

    /. O'se$#e t&e output '! +eep%"g CLR910 S190 S9.

    . e$%f! !ou$ $esu(ts %t& t&e t$ut& ta'(e

    RESULT8

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    ECAD LAB

    SOFT6ARE

    E3ERI2ENTS

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    ECAD LAB

    7. LOGIC GATES

    AI28 To s%u(ate t&e Log%) *ates.

    AARATUS8

    1. Copute$ S!ste

    2. %(%"6 ISE 1.13. Moe(s% .=' S%u(ato$ 

    AN GATE (IC 9:;

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    OR GATE (IC 9:>?- EFINITION8

    A Lo"c OR Gte o$ I")(us%#e;OR gate %s a t!pe of %g%ta( (og%) gate t&at &as a" output &%)&

    %s "o$a((! at (og%) (e#e( 44 a" o"(! goes 4HI*H4 to a (og%) (e#e( 414 &e" o"e o$ o$e of %ts

    %"puts a$e at (og%) (e#e( 414. T&e output0 of a Lo"c OR Gte o"(! $etu$"s 4LO54 aga%" &e" ALL

    of %ts %"puts a$e at a (og%) (e#e( 44. T&e (og%) o$ Boo(ea" e6p$ess%o" g%#e" fo$ a (og%) OR gate %s t&at

    fo$  Logical Addition  &%)& %s e"ote '! a p(us s%g"0 7 < 8 g%#%"g us t&e Boo(ea" e6p$ess%o"

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    NOT GATE (IC 9:;:- EFINITION8

    T&e %g%ta( Lo"c NOT Gte %s t&e ost 'as%) of a(( t&e (og%)a( gates a" %s soet%es

    $efe$$e to as a" I!vert"! =/%%er o$ s%p(! a ""t' I!verter. It %s a s%"g(e %"put e#%)e &%)& &as

    a" output (e#e( t&at %s "o$a((! at (og%) (e#e( 414 a" goes 4LO54 to a (og%) (e#e( 44 &e" %ts s%"g(e

    %"put %s at (og%) (e#e( 4140 %" ot&e$ o$s %t 4%"#e$ts4 7)op(ee"ts8 %ts %"put s%g"a(. T&e output f$o a

     NOT gate o"(! $etu$"s 4HI*H4 aga%" &e" %ts %"put %s at (og%) (e#e( 44 g%#%"g us t&e Boo(ea"

    e6p$ess%o" of: A 9 .

    LOGIC IAGRA28

    TRUTH TA=LE8

    VHL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    entity NOTGATE is  Port A ! in STD_LOGIC;

    C ! out STD_LOGIC#;en$ NOTGATE;

    ar%&ite%ture Data'lo( o' NOTGATE isbe)in

    C*+ NOT A;en$ Data'lo(;

    NAN GATE (IC 9:;;- EFINITION8

    T&e Lo"c NAN Gte  %s a )o'%"at%o" of t&e %g%ta( (og%) AND gate %t& t&at of a"%"#e$te$ o$ NOT gate )o""e)te toget&e$ %" se$%es. T&e NAND 7Not ; AND8 gate &as a" output t&at %s

    "o$a((! at (og%) (e#e( 414 a" o"(! goes 4LO54 to (og%) (e#e( 44 &e" ALL of %ts %"puts a$e at

    (og%) (e#e( 414. T&e Lo"c NAN Gte %s t&e $e#e$se o$ 4Complementary4 fo$ of t&e AND gate e

    &a#e see" p$e#%ous(!.

    LOGIC IAGRA28

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    ECAD LAB

    TRUTH TA=LE8

    VHL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    entity NANDGATE is

      Port A ! in STD_LOGIC;" ! in STD_LOGIC;C ! out STD_LOGIC#;

    en$ NANDGATE;

    ar%&ite%ture Data'lo( o' NANDGATE isbe)in

    C*+A NAND ";en$ Data'lo(;

    NOR GATE (IC 9:;?- EFINITION8

    T&e Lo"c NOR Gte o$ I")(us%#e;NOR gate %s a )o'%"at%o" of t&e %g%ta( (og%) OR gate%t& t&at of a" %"#e$te$ o$ NOT gate )o""e)te toget&e$ %" se$%es. T&e NOR 7Not ; OR8 gate &as a"

    output t&at %s "o$a((! at (og%) (e#e( 414 a" o"(! goes 4LO54 to (og%) (e#e( 44 &e" ANY of %ts

    %"puts a$e at (og%) (e#e( 414. T&e Lo"c NOR Gte %s t&e $e#e$se o$ 4Complementary4 fo$ of t&e OR 

    gate e &a#e see" p$e#%ous(!.

    LOGIC IAGRA28

    TRUTH TA=LE8

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    ECAD LAB

    VHL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    entity NO,GATE is  Port A ! in STD_LOGIC;

    " ! in STD_LOGIC;C ! out STD_LOGIC#;

    en$ NO,GATE;

    ar%&ite%ture Data'lo( o' NO,GATE isbe)in

    C*+A NO, ";en$ Data'lo(;

    3OR GATE (IC 9:

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    ECAD LAB

    T&e E4c'/1"ve5NOR Gte fu")t%o" o$ E6;NOR fo$ s&o$t0 %s a %g%ta( (og%) gate t&at %s t&e

    $e#e$se o$ )op(ee"ta$! fo$ of t&e E6)(us%#e;OR. T&e E6)(us%#e;NOR gate %s a )o'%"at%o" of 

    t&e E6)(us%#e;OR gate a" t&e NOT gate. It &as a" output t&at %s "o$a((! at (og%) (e#e( 44 &e"

    ANY of %ts %"puts a$e at (og%) (e#e( 414.

    LOGIC IAGRA28

    TRUTH TA=LE8

    VHL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    entity -NO,GATE is  Port A ! in STD_LOGIC;

    " ! in STD_LOGIC;C ! out STD_LOGIC#;en$ -NO,GATE;

    ar%&ite%ture Data'lo( o' -O,GATE isbe)in

    C*+A -NO, ";en$ Data'lo(;

    RESULT8

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    ECAD LAB

    ?. > to < ECOER 9:7><

    AI28 To s%u(ate a" s!"t&es%Je 3 to / e)oe$ 7,-13/8.

    AARATUS8 1. Copute$ S!ste

    2. %(%"6 ISE 1.1

    3. Moe(s% .=' S%u(ato$ 

    THEORY8

    A e)oe$ %s a u(t%p(e;%"put0 u(t%p(e output (og%) )%$)u%t t&at )o"#e$ts )oe %"puts %"to

    )oe outputs0 &e$e t&e %p"put a" output )oes a$e %ffe$e"t. T&e %"put )oe ge"e$a((! &as fee$ 

     '%ts t&a" t&e output )oe.

    IN IAGRA28

    FUNCTION TA=LE:

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    ECAD LAB

    VHL COE (ATAFLO6 2OEL-library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    entity$e%o$er_$ is  Port )1)/a_l)/b_l ! in STD_LOGIC;

    a ! in STD_LOGIC_0ECTO, / $o(nto #;y_l ! out STD_LOGIC_0ECTO, to 2##;

    en$$e%o$er_$;

    ar%&ite%ture $ata'lo( o' $e%o$er_$ issi)nal y! st$_lo)i%_3e%tor to 2#;

    be)in(it& a sele%t y*+

    1111111 (&en 1111111 (&en 11111111 (&en 11111111 (&en 111111111 (&en 11111111 (&en 111111111 (&en 111111111 (&en 11111111111 (&en ot&ers;

    y_l*+ y (&en )1 an$ not )/a_l# an$ not )/b_l## + 515 else11111111;en$ $ata'lo(;

    VHL COE (=EHAVIORAL 2OEL-8library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    entity$e%o$er_b is  Port )1)/a_l)/b_l ! in STD_LOGIC;

    a ! in STD_LOGIC_0ECTO, / $o(nto #;y_l ! out STD_LOGIC_0ECTO, to 2##;

    en$$e%o$er_b;

    ar%&ite%ture "e&a3ioral o' $e%o$er_b issi)nal y ! st$_lo)i%_3e%tor to 2#;

    be)inro%ess )1)/a_l)/b_lya#

    be)in %ase a is(&en +7 y *+ 1111111;(&en 1 +7 y *+ 1111111;(&en 1 +7 y *+ 1111111;(&en 11 +7 y *+ 1111111;(&en 1 +7 y *+ 1111111;(&en 11 +7 y *+ 1111111;(&en 11 +7 y *+ 1111111;(&en 111 +7 y *+ 1111111;(&en ot&ers +7 y *+ 11111111;en$ %ase;

    i' )1 an$ not )/a_l# an$ not )/b_l## + 515 t&en y_l*+ y;

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    ECAD LAB

    elsey_l*+ 11111111;en$ i';en$ ro%ess;en$ "e&a3ioral;

    RESULT8

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    ECAD LAB

    >.

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    ECAD LAB

    VHL COE (ATAFLO6 2OEL-8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_unsi)ne$.ALL;

    entity8ultile9er_$ is  Port en_L ! in STD_LOGIC;

    s ! in STD_LOGIC_0ECTO, / $o(nto #;$ ! in STD_LOGIC_0ECTO, to 2#;y !inout STD_LOGIC;y_l ! out STD_LOGIC#;

    en$8ultile9er_$;

    ar%&ite%ture $ata'lo( o' 8ultile9er_$ issi)nal 9 ! st$_lo)i%;

    be)in(it& s sele%t 9 *+

    $# (&en $1# (&en 1$/# (&en 1$:# (&en 11$4# (&en 1$# (&en 11$6# (&en 11$2# (&en 1115

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    ECAD LAB

    (&en 11 +7 9 *+ $#;(&en 11 +7 9 *+ $6#;(&en 111 +7 9 *+ $2#;(&en ot&ers +7 9 *+ 5

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    ECAD LAB

    VHL COE:

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    entity$e8u9 is

    ort %1 %/! in st$_lo)i%; ?? $ata inuts)1_l )/_l! in st$_lo)i%; ??enable inutssel! in st$_lo)i%_3e%tor1 $o(nto #; ??sele%t inuty1 y/! out st$_lo)i%_3e%tor: $o(nto ##; ??outut

    en$$e8u9;

    ar%&ite%ture$e8u9 o' $e8u9 isbe)in

    ro%ess %1 %/ )1_l )/_l sel#be)in

    y1 *+ 1111; y/*+ 1111; ??initili@e oututi' )1_l + 55# t&en

    %asesel is(&en +7 y1# *+ %1;(&en 1 +7 y11# *+ %1;(&en 1 +7 y1/# *+ %1;(&en 11 +7 y1:# *+ %1;(&en ot&ers+7 null;en$ %ase;

    en$ i';

    i' )/_l + 55# t&en%asesel is(&en +7 y/# *+ %/;(&en 1 +7 y/1# *+ %/;

    (&en 1 +7 y//# *+ %/;(&en 11 +7 y/:# *+ %/;(&en ot&ers+7 null;en$ %ase;

    en$ i';en$ ro%ess;

    en$$e8u9;

    RESULT8

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    ECAD LAB

    :. :5 ="t CO2ARATOR 9:

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    ECAD LAB

    LOGIC IAGRA28

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    ECAD LAB

    VHL =EHAVIORAL COE8

    library IEEE;use IEEE.st$_lo)i%_1164.all;

    entity %o8 is

    ort altbin! in STD_LOGIC;aebin! in STD_LOGIC;a)tbin! in STD_LOGIC;a! in STD_LOGIC_0ECTO, : $o(nto #;b! in STD_LOGIC_0ECTO, : $o(nto #;a)tbout! out STD_LOGIC;aebout! out STD_LOGIC;altbout! out STD_LOGIC#;

    en$ %o8;ar%&ite%ture %o8 o' %o8 isbe)in

    ro%essaba)tbinaebinaltbin#be)in

    a)tbout*+55; --initializes the outputs to ‘0’aebout*+55;altbout*+55;

    i'aebin+515 t&eni' a+b t&en aebout*+515;elsi' a7b t&en a)tbout*+515;elsi' a*b# t&en altbout*+515;

    en$ i';elsi' altbinB+a)tbin#t&en

    a)tbout*+a)tbin;altbout*+altbin;

    en$ i';en$ ro%ess ;

    en$ Co8;

    RESULT8

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    ECAD LAB

    . FLI5FLO 9:9:

    AI28 To s%u(ate a" s!"t&es%Je D (%p;(op 7,-,-8.

    AARATUS8 1. Copute$ S!ste

    2. %(%"6 ISE 1.13. Moe(s% .=' S%u(ato$ 

    THEORY8

    T&ese e#%)e )o"ta%"sto %"epe"e"t D;t!pe pos%t%#e ege t$%gge$e f(%p;f(ops. A (o (e#e(

    at &e p$eset o$ )(ea$ %"puts set o$ $esets t&e output $ega$(ess of t&e (e#e(s of t&e ot&e$ %"puts. 5&e"

     p$eset a" )(ea$ a$e %"a)t%#e0 ata at t&e D f(%p;f(op %"puta$e t$a"sfe$$e to t&e output o" t&e pos%t%#e

    go%"g ege of t&e )(o)+ pu(se.

    FUNCTION TA=LE8

    LOGIC IAGRA28

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    ECAD LAB

    VHL =EHAVIORAL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    entity $''2424 is  Port %l1%l/%lr_l1%lr_l/r_l1r_l/ $1 $/ ! in STD_LOGIC;  1bar1 / bar/ ! out STD_LOGIC#;en$ $''2424;

    ar%&ite%ture "e&a3ioral o' $''2424 isbe)in

    1! ro%ess %l1 %lr_l1 r_l1 $1#be)in

    i' r_l1 +55 an$ %lr_l1 +55# t&en 1*+ 515; bar1 *+ 515;elsi' r_l1 + 55# t&en 1*+ 515; bar1 *+ 55;elsi' %lr_l1 + 55# t&en 1*+ 55; bar1 *+ 515;elsi' r_l1 +515 an$ %lr_l1 +515 an$ %l15e3ent an$ %l1 +515## t&en 1*+ $1; bar1 *+ not $1;en$ i';en$ ro%ess;

    /! ro%ess %l/ %lr_l/ r_l/ $/#be)in

    i' r_l/ +55 an$ %lr_l/ +55# t&en /*+ 515; bar/ *+ 515;elsi' r_l/ + 55# t&en /*+ 515; bar/ *+ 55;elsi' %lr_l/ + 55# t&en /*+ 55; bar/ *+ 515;elsi' r_l/ +515 an$ %lr_l/ +515 an$ %l/5e3ent an$ %l/ + 515##

    t&en /*+ $/; bar/ *+ not $/;en$ i';en$ ro%ess;

    en$ "e&a3ioral;

    RESULT8

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    ECAD LAB

    @. ECAE COUNTER 9:B;

    AI28 To s%u(ate a" s!"t&es%Je e)ae )ou"te$ 7,-8.

    AARATUS8 1. Copute$ S!ste

    2. %(%"6 ISE 1.1

    3. Moe(s% .=' S%u(ato$ THEORY8

    Ea)& of t&ese o"o(%t&%) )ou"te$s )o"ta%"s fou$ aste$ s(a#e f(%p;f(ops a" a%t%o"a( gat%"g

    to p$o#%e a %#%e;'! to )ou"te$ a" a t&$ee;stage '%"a$! )ou"te$ fo$ &%)& t&e )ou"t )!)(e (e"gt& %s

    %#%e;'!;f%#e fo$ t&e DM,-LS. A(( of t&ese )ou"te$s &a#e a gate Je$o $eset a" t&e DM,-LS

    a(so &as gate set;to;"%"e %"puts fo$ use %" BCD "%"es )op(ee"t app(%)at%o"s. To use t&e%$ 

    a6%u )ou"t (e"gt& 7e)ae o$ fou$ '%t '%"a$!80 t&e B %"put %s )o""e)te to t&e A output. T&e

    %"put )ou"t pu(ses a$e app(%e to %"put A a" t&e outputs a$e as es)$%'e %" t&e app$op$%ate t$ut& ta'(e.

    A s!et$%)a( %#%e;'!;te" )ou"t )a" 'e o'ta%"e f$o t&e DM,-LS )ou"te$s '! )o""e)t%"g t&e

    D output to t&e A %"put a" app(!%"g t&e %"put )ou"t to t&e B %"put &%)& g%#es a %#%e;'!;te"

    s>ua$e a#e at output A.

    RESETCOUNT TRUTH TA=LE8

    TRUTH TA=LE8

    LOGIC IAGRA28

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    ECAD LAB

    VHL =EHAVIORAL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;useieee.st$_lo)i%_unsi)ne$.all;

    entity$e%_%ounter is

      Port %l ! in STD_LOGIC;  r_1 r_/ r_1 r_/ ! in STD_LOGIC; ! out STD_LOGIC_0ECTO, : $o(nto ##;

    en$$e%_%ounter;

    ar%&ite%ture"e&a3ioral o' $e%_%ounter issi)nal %ount! st$_lo)i%_3e%tor : $o(nto #;

    be)in

    ro%ess %l r_1 r_/ r_1 r_/ %ount#be)in

    i' r_1 an$ r_/#+ 515 t&en %ount *+ ;

    elsi' r_1 an$ r_/#+ 515 t&en %ount *+ 11;elsi' %l5e3ent an$ %l + 55# t&en %ount *+ %ount 1;i' %ount + # t&en %ount *+ ;en$ i';en$ i';

    *+ %ount;en$ ro%ess;en$"e&a3ioral;

    RESULT8

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    ECAD LAB

    9. :5=IT =INARY COUNTER 9:B>

    AI28 To s%u(ate a" s!"t&es%Je -;'%t '%"a$! )ou"te$ 7,-38.

    AARATUS8 1. Copute$ S!ste

    2. %(%"6 ISE 1.1

    3. Moe(s% .=' S%u(ato$ THEORY8

    T&e )ou"te$ )o"ta%"s fou$ aste$ s(a#e f(%p;f(ops a" a%t%o"a( gat%"g to p$o#%e a %#%e;'!

    to )ou"te$ a" a t&$ee;stage '%"a$! )ou"te$ fo$ &%)& t&e )ou"t )!)(e (e"gt& %s %#%e;'!;e%g&t fo$ 

    t&e 3A. A(( of t&ese )ou"te$s &a#e a gate Je$o $eset.

    To use t&e%$ a6%u )ou"t (e"gt& 7e)ae o$ fou$;'%t '%"a$!80 t&e B %"put %s )o""e)te to

    t&e A output. T&e %"put )ou"t pu(ses a$e app(%e to %"put A a" t&e outputs a$e as es)$%'e %" t&e

    app$op$%ate t$ut& ta'(e. A s!et$%)a( %#%e;'!;te" )ou"t )a" 'e o'ta%"e f$o t&e A )ou"te$s '!

    )o""e)t%"g t&e D output to t&e A %"put a" app(!%"g t&e %"put )ou"t to t&e B %"put &%)& g%#es a

    %#%e;'!;te" s>ua$e a#e at output A.

    RESETCOUNT TRUTH TA=LE8

    TRUTH TA=LE8

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    ECAD LAB

    LOGIC IAGRA28

    VHL =EHAVIORAL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_unsi)ne$.ALL;

    entity %ounter is  Port r_1 r_/ %l ! in STD_LOGIC;

    ! out STD_LOGIC_0ECTO, : $o(nto ##;en$ %ounter;

    ar%&ite%ture"e&a3ioral o' %ounter issi)nal %ount! STD_LOGIC_0ECTO, : $o(nto #;

    be)in

    ro%ess r_1 r_/ %l %ount#be)in

    i' r_1 + 515 an$ r_/ + 515# t&en %ount *+ ;

    elsi' %l5e3ent an$ %l + 515# t&eni' r_1 + 55# t&en%ount*+ %ount 1;elsi' r_/ + 55# t&en%ount*+ %ount 1;en$ i';en$ i';

      *+ %ount;en$ ro%ess;en$"e&a3ioral;

    RESULT8

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    ECAD LAB

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    VHL =EHAVIORAL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_unsi)ne$.ALL;

    entity usr2414 is  Port %l %lr_l lin rin ! in STD_LOGIC;

    s ! in STD_LOGIC_0ECTO, 1 $o(nto #;$ ! in STD_LOGIC_0ECTO, : $o(nto #; !inout STD_LOGIC_0ECTO, : $o(nto ##;

    en$ usr2414;

    ar%&ite%ture"e&a3ioral o' usr2414 isbe)in

    ro%ess %l %lr_l lin rin s $ #be)in

    i'%lr_l + 55 t&en *+ ;elsi' %l5e3ent an$ %l + 515# t&en

    %ase s is(&en +7 *+ ;(&en 1 +7 *+ rinF : $o(nto 1#;(&en 1 +7 *+ / $o(nto # Flin;(&en 11 +7 *+ $;(&en ot&ers +7 *+

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    ECAD LAB

    B. RA2 (9:7

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    ECAD LAB

    VHL =EHAVIORAL COE8library IEEE;use IEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_unsi)ne$.ALL;use IEEE.STD_LOGIC_A,IT.ALL;

    entity D8241H is  Port a ! in STD_LOGIC_0ECTO, : $o(nto #;

    $ ! in STD_LOGIC_0ECTO, : $o(nto #;%s_bar ! in STD_LOGIC;(e_bar ! in STD_LOGIC; ! out STD_LOGIC_0ECTO, : $o(nto ##;

    en$ D8241H;

    ar%&ite%ture ,a8 o' D8241H istyera8_tye is array to 1# o' STD_LOGIC_0ECTO, : $o(nto #;

    si)nalte8!,a8_tye;be)in

    (rite! ro%ess%s_bar(e_bara$#be)ini' %s_bar+55 an$ (e_bar+55# t&en te8%on3_inte)era##*+$;en$ i';

    en$ ro%ess (rite;rea$ ! ro%ess %s_bar(e_bara$#3ariable 31!st$_lo)i%_3e%tor : $o(nto #;be)ini' %s_bar+55 an$ (e_bar +515# t&en 31!+te8%on3_inte)era##;else31!+315ran)e +755#;en$ i';*+ 31;en$ ro%ess rea$;en$ ,a8;

    RESULT8

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    ECAD LAB

    7;.STAC+ AN UEUE I2LE2ENTATION USING RA2

    AI28 To 5$%te T&e HDL Coe o$ Ip(ee"t%"g Sta)+ A" ueue s%"g RAM.

    AARATUS8 1. Copute$ S!ste

    2. %(%"6 ISE 1.13. Moe(s% .=' S%u(ato$ 

    ESCRITION8

    STAC+8A sta)+ %s s%p(! a Last %" %$st out 7LIO8 eo$! st$u)tu$e. E#e$! sta)+ &as a sta)+ 

     po%"te$ 7SP8 &%)& a)ts as a" a$ess fo$ a))ess%"g t&e e(ee"ts. But "o$a((! t&e use$ of t&e sta)+ %s

    "ot )o")e$"e %t& t&e a'so(ute a$ess of t&e sta)+ &e %s o"(! )o")e$"e %t& t&e PSH a" POP

    %"st$u)t%o"s.

    UEUE8A >ueue %s a )o"ta%"e$ of o'Qe)ts 7a (%"ea$ )o((e)t%o"8 t&at a$e %"se$te a" $eo#e

    a))o$%"g to t&e f%$st;%" f%$st;out 7IO8 p$%")%p(e. A" e6)e((e"t e6ap(e of a >ueue %s a (%"e of 

    stue"ts %" t&e foo )ou$t of t&e C. Ne a%t%o"s to a (%"e ae to t&e 'a)+ of t&e >ueue0 &%(e$eo#a( 7o$ se$#%"g8 &appe"s %" t&e f$o"t. I" t&e >ueue o"(! to ope$at%o"s a$e a((oe e">ueue a"

    e>ueue. E">ueue ea"s to %"se$t a" %te %"to t&e 'a)+ of t&e >ueue0 e>ueue ea"s $eo#%"g t&e

    f$o"t %te. T&e p%)tu$e eo"st$ates t&e IO a))ess. T&e %ffe$e")e 'etee" sta)+s a" >ueues %s %"

    $eo#%"g. I" a sta)+ e $eo#e t&e %te t&e ost $e)e"t(! ae %" a >ueue0 e $eo#e t&e %te t&e

    (east $e)e"t(! ae.

    VHL COE8

    7- I2LE2ENTING A FIFO UEUE IN VHL

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    use IEEE.STD_LOGIC_A,IT.ALL;use IEEE.STD_LOGIC_

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    ECAD LAB

    8e8ory%on3_inte)er(ritetr## *+ $atain; (ritetr*+ (ritetr 515; ??oints to ne9t a$$ress.en$ i';

    i'rea$tr + 1111# t&en ??resettin) rea$ ointer.rea$tr*+ ;en$ i';

    i'(ritetr + 1111# t&en'ull*+515;(ritetr*+ ;else 'ull *+55;en$ i';

    i'(ritetr + # t&ene8ty*+515;elsee8ty*+55;en$ i';

    en$ ro%ess;en$ "e&a3ioral;

    ?- I2LE2ENTING A STAC+ IN VHL

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;

    entity sta% isortCl ! in st$_lo)i%; ??Clo% 'or t&e sta%.

    Enable ! in st$_lo)i%;Data_In ! in st$_lo)i%_3e%tor: $o(nto #;Data_Out ! out st$_lo)i%_3e%tor: $o(nto #;P

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    ECAD LAB

    P

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    ECAD LAB

    77. ALU (9:>u%$ee"ts

    • Pe$fo$s s%6 a$%t&et%) a" (og%) fu")t%o"s

    • Se(e)ta'(e LO5 7)(ea$8 a" HI*H 7p$eset8 fu")t%o"s

     

    Ca$$! ge"e$ate a" p$opagate outputs fo$ use %t& )a$$!.

    FUNCTION TA=LE8

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    ECAD LAB

    VHL =EHAVIORAL COE8

    library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_