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A SIENNA GROUP COMPANY
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Sienna Ecad _2015_Ver1

Aug 17, 2015

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Shashi Gowda
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Page 1: Sienna Ecad _2015_Ver1

A SIENNA GROUP COMPANY

Page 2: Sienna Ecad _2015_Ver1

GROUP CAPABILITIES

Cable Assembly

& Wire Harness

Metal Components

Plastics System Integration

Magnetics

Precision Sheet Metal

PCB Assembly

Page 3: Sienna Ecad _2015_Ver1

GLOBAL LOCATIONS

Batesburg, SC

Atlanta, GA

Fremont, CA East Windsor, CT

Chennai, IN

Bangalore, IN

Design &

Manufacturing

Milan, Italy

Joint Venture Partner

Future Expansion

South Africa

Seattle, WA

Page 4: Sienna Ecad _2015_Ver1

CERTIFIED QUALITY SYSTEMS

ISO/TS 16949

Sienna / Avalon

ISO 9001/TL 9000

Sienna / Avalon

ISO 27001

Emantras

ISO 13485

Sienna Atlanta ISO 9001:2008

Sienna Corporation

ISO 9001:2008

Sienna ECAD AS9100

Avalon / Avatar

Page 5: Sienna Ecad _2015_Ver1

High End

PCB Design

Engineering

Expedite delivery options

>10,000 layouts Gerbered

ISO Certified

Robust IT Setup for Data Security

Multi Tool Expertise

>97% First time Right Designs

150 Engineers at 3 Indian Locations

Onsite Support 18x6 support

SIENNA ECAD

Library

DFX

Prototype

Build

Complex

Layout

Simulation &

Analysis

Page 6: Sienna Ecad _2015_Ver1

MAJOR CUSTOMERS

Communication Semiconductor Aerospace/

Power

Medical/

Industrial/

Automotive

Engineering

Centers

Singapore Aerospace

Page 7: Sienna Ecad _2015_Ver1

Awards

2011 Best paper Award in EDA 360 – by Cadence, India

“Addressing Challenges of high-speed design Technology”

2012 Secured - Best Embedded Software Award from UTAS (Goodrich, India)

2013 Best paper & U Innovate Award – U2U, Mentor Graphics, India

“Fail safe design using SI-PI-Thermal Co-simulation”

2010 Mentor Graphics Technology Leadership Awards - Worldwide

Category: Telecom, Network Controllers, Line Cards

2009 Mentor Graphics Technology Leadership Awards - Worldwide

Category : Computers, Blade & Servers, Memory Systems

Page 8: Sienna Ecad _2015_Ver1

PCB DESIGN - MARKET DIFFERENTIATORS

• Over 7000 complex and HDI designs completed in 17 year period

• Innovative design methods in Fine Pitch Micro BGA designs

• Handled fine pitch BGA upto 0.37mm using 2 mil/ 2mil track/spacings

• Design technologies with stacked µ via HDI design

• Embedded passives and Hybrid PCB materials usage

• Design analysis and implementation of timing critical designs

• Multi-board SI analysis

• High bit rate (~ 6.5Gbps) analysis for serial I/O designs

• Signal performance analysis for BER, EYE opening

• Board Level and System Level Thermal analysis

• DC drop analysis in power supply rails due to copper losses

• ISO CERTIFIED

Page 9: Sienna Ecad _2015_Ver1

Projects % v/s No. of Layers

80

60

40

20

0

47 37

15 1

2 to 8 10 to 18 20 to 24 26 to 72

TECHNOLOGY

• Fine pitch BGA upto 0.37mm, 2mil/2mil technology

• Layers up to 72

• Components more than 10000, Connections more than 97000

• Stringent Thermal, Mechanical and Electrical requirements

• Flexi rigid designs, Embedded passives, Composite stackups

HIGH SPEED DIGITAL , RF , POWER , MIXED SIGNAL DESIGNS

• Very tight timing and skew requirements

• Interfaces – DDR3,SFP, Ethernet ,HDMI,USB

• Onboard printed Antennas for GSM,GPS & GPRS band

HDI DESIGN CAPABILITY

• Design for optimum volume production yields for fine pitch BGA’s

• Small form factor designs

Page 10: Sienna Ecad _2015_Ver1

PCB Design Process

ROUTING

Fan out, critical

signal routing,

approval, route

completion

POST ROUTE

ANALYSIS

Post route SI,

EMI/EMC analysis,

Thermal analysis

POST PROCESS

Final design approval

Gerber generation,

CAM validation,

PLACEMENT

Verification by

Customer,

Assembly team.

Thermal Team, SI

team

PRE ANALYSIS

Data Preparation,

Thermal Analysis,

Pre route SI

Analysis

PLANE CREATION

CONSTRAINT

SETTING

IPC – 7351B

COMPLIANT

Web based library

request – Online

status review

BOARD

MECHANICAL

Critical part

verification using

Pro E

STACKUP

Build as per

impedance

requirement,

verification with

FAB house

Inputs from customer

collected using customer

Input checklist

Project Tracker Creation –

Comprising of Project

team , issue tracker,

Schedule tracker

Design Review – Webex,

Schedule conference calls

by remote screen sharing

STACKUP MECHANICAL LIBRARY

CO

MP

LET

ION

EX

EC

UT

ION

IN

ITIA

TIO

N Layo

ut

Desi

gn

Pro

cess

Page 11: Sienna Ecad _2015_Ver1

• 275 Fabrication checks

• 250 Assembly checks

• 100 Advanced substrate checks

• 40 Microvia checks

• 30 Assembly panel checks

Top Business Pressures Driving Improvements in PCB Design

789 DFM

Checks

0% 5% 10% 15% 20% 25% 30% 35% 40% 45%

Reduced development budgets

Demand for feature-rich products

Demand for higher quality products

Demand for lower cost products

Need to launch products quality

Issue Pin pitch

mismatch

Issue type Critical

Assembly Issue

Pin pitch mismatch at

heel side leaving no

pad for soldering

Solution

Footprint shall be

validated against

datasheet & IPC land

pattern standards

Comprehensive DFX Service - Valor

Page 12: Sienna Ecad _2015_Ver1

Complex Layout Example - 72 Layer Design

Layout Statistics: Layers - 72

Components -6627

Connections – 97520

Board size – 24.5”X21.4”

Challenges Design with 32 signal layers

16 BGAs with 5452 pins each

Route exits and length matching for BGAs

Page 13: Sienna Ecad _2015_Ver1

Complex Layout

Video Card -12 Layers, 646 Components, 529 PIN BGA, 2246 connections, 2.9"x3.5"

Mother Board -16 Layers, 5061 components, 2x2011 PIN BGA, 20870 connections, 23"x8.4"

Carrier Card-18 Layers, 1902 Components, 1512 PIN BGA, 8415 connections, 9.19"x6.3"

Page 14: Sienna Ecad _2015_Ver1

Tool Expertise

Mentor PADS, Mentor Expedition (Extreme Design),Board Station

Cadence Allegro, Orcad Layout, Altium Designer

Orcad CIS, Dx Designer/Databook, Concept HDL

Power Logic , Design Architect , Design Capture Schematic &

Layout

Valor Enterprise, Lavenir View Master, CAM350 DFM

Betasoft, Flotherm

Hyperlynx, Cadence Spectraquest, CST studio

Mentor Hyperlynx SI GHz, 3D EM Engine, Hyperlynx PI, Specctraquest SI

Analysis

Thermal EMI SI

CREO , Relex (Windchill Reliability), Cable Harness XC Others

Page 15: Sienna Ecad _2015_Ver1

Smart Library

Schematic Symbol PCB Footprint (IPC 7351B based )

3D Part VPL Part

Page 16: Sienna Ecad _2015_Ver1

Simulation & Analysis

Power Integrity Thermal Analysis Signal Integrity

Sienna ECAD Analysis Division

Net Level EMI

Page 17: Sienna Ecad _2015_Ver1

Signal Integrity

Interfaces handled

180 FPGA’s, CPLD’s, ASIC’s, Proces & Micro controllers

52 Ethernet, MMI, SGMII & RGMII

130 DDR, DDR2, DDR3, QDR’s

90 Flash, PROM, SRAM, DPRAM

16 Backplane

32 ADC & DAC Interfaces

40 XLAUR, RXAUI, XUAI & Hyperlink Interface

10 XFI & SFP

8 USB1, USB2, USB3 & HDMI

60 PCI1, PCI2, PCI3 & SATA, Rocket IOs

Worked on Latest Si IP Platform on Ser Des Interface

at Data Rates upto 28Gbps.

Page 18: Sienna Ecad _2015_Ver1

Co Simulation

Fail-safe designs using SI-PI-Thermal Co-Simulation

Page 19: Sienna Ecad _2015_Ver1

Power Integrity Analysis Capabilities

DC Drop analysis Plane Noise Current Density Plot

Page 20: Sienna Ecad _2015_Ver1

System / Board Level Thermal Analysis

Page 21: Sienna Ecad _2015_Ver1

System Engineering

System Engineering

Group

Hardware Design

Cable Harness

Design Embedded

Software

Sustaining Engg

System Integration

Support

Dedicated

Team

Pre Compliance

Testing Support Re Engineering

Page 22: Sienna Ecad _2015_Ver1

Hardware Design

Configurable router supporting

Ethernet, Wi-Fi, and Cellular 2G, 3G,

and 4G cellular networks – Firmware

Development

M2M Gateway

Gateways for payment terminals, POS

payment controllers, check readers and

ATMs –Firmware Development

Payment Gateway

• 10/100/1000 Mbps Managed Ethernet Switches.

• Boards with 10Gbps Ethernet with interfaces XAUI, XFI, SFP+, XFP, XPAK

• Fiber channel host bus adapter for 1/2/4 Gbps

• SERDES (Fiber Channel, PCIe) characterization board with SMA connectors, ASIC emulation

board with 9 FPGA (Xilinx – Virtex4) devices

• Wireless products using GPS, GSM/GPRS, Bluetooth, WiFi, ZigBee, Z-Wave, 900/2.4 GHz ISM

Band, DECT and DVB-H modules

• M2M gateways

• PCI E Architecture designs

Page 23: Sienna Ecad _2015_Ver1

Sustaining Engineering

Monitoring and directing technical service procedures for hardware products.

• Manage minor product upgrades due to EOL

• Manage all EMS activity support to ensure product deliveries are as per planned

schedule.

• Analyzing and documenting potential customer requirements and translates them into

hardware development plans.

• Managing all aspects of the change request process.

• Describes methods and considerations for estimating costs for request fulfillment

Page 24: Sienna Ecad _2015_Ver1

Embedded Software Expertise

Linux Device Driver development

Linux internals Memory management, Process management, IPC

Linux multithreaded application

Linux Bootloader ( Bootstrap & u-boot )

Managed Ethernet switch which supports TCP/IP, VLAN, SNMP, RMON, RSTP, DHCP, PPP,

HTTP, Telnet and CLI

Protocol stack development such as : STP, IEEE802.3ad/LACP, SNTP Client.

Routing Protocols – RIP, OSPF

IP Security and IP tables

Ethernet traffic classifications based on L2-L4 parameters

System development using multiple RTOS

Development of system using various wireless communication protocols

Development of network configuring and monitoring protocols.

Development of systems using Industrial Communication Protocols such as I2C, SPI, and UART

Development of file systems and media drivers such as USB, SD Card and Flash

Page 25: Sienna Ecad _2015_Ver1

Prototype Build

PCBA Capabilities

POP Assemblies

BGA Assemblies

Page 26: Sienna Ecad _2015_Ver1

Prototype Build

• PCB Thickness : upto 4.1 mm

• PCB Layers handled : 24 Layers

• POP (Package on Package assembly):

0.4mm & 0.6mm pitch

• BGA’s: -Pitch : 0.4mm

-Ball Size : 0.2 mm

-No of Balls: 2800

• QFP’s - Pitch: 0.38mm

• Discrete Packages: Up to 01005

( 0.14mm X 0.20mm)

• Place component package 0201 at 45degree

angle.

• 52 BGAs in an Assembly

• Max Components / PCBA : 10k

Complexities Handled PCB Assemblies

• Hi-Complex double-sided PCB assembly

• High Mix, Low to medium volume assemblies

• ROHS and conventional process

• SMT, Through-Hole and mix technology

assemblies, Backplanes

• Automated Optical Inspection (AOI)

• In-Circuit and Flying probe test

• Design for manufacturability reviews and

Yield analysis

• IPC Standards Class 2 and Class 3, MILSPEC

• Latest component technologies

• Conformal coating, Encapsulation

• Total traceability

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Page 27: Sienna Ecad _2015_Ver1

Facilities

Unit 1 : Banashankari,

Bangalore (Design)

Unit 2: Whitefield, Bangalore

(Design) Unit 3: Hubli

(Design)

Bangalore , INDIA (NPI Build) Atlanta , U.S (NPI Build)

Page 28: Sienna Ecad _2015_Ver1

Cable Harness Design

Custom cable & wire harness assembly

• Complex cable harness

• Coaxial

• Electro mechanical assemblies

• Stainless and synthetic overbraids

• Flat ribbon cables

• RF Cables

• Over-molding

• Custom harnesses

Page 29: Sienna Ecad _2015_Ver1

Corporate Training

Areas of Training

PCB Design Engineering Process

PCB Design Standards

CAD Tool Based Training

Signal Integrity

Power Integrity

DFF/DFA

Companies Trained

Page 30: Sienna Ecad _2015_Ver1

Partners

Valor NPI – DFM

Software

www.mentor.com

3PLD SOLUTIONS

www.tabula.com