Ecad Record

8/11/2019 Ecad Record

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R R SCOLLEGE OF ENGINEERING & TECHNOLOGY, Muthangi

Exp no: __________ Date: ____________ Page No:

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INTRODUCTION TO VHDL

What is VHDL?

VHDL stands for very high-speed integrated circuit hardware description

language which is one of the programming language used to model a digital

system by dataow, behavioral and structural style of modeling. This language

was rst introduced in !"#! for the department of Defense $DoD% under

the VH&'( program. 'n !"#) '*+, Teas instruments and 'ntermetrics started to

develop this language. 'n !"# VHDL ./ version was released. 'n !"# '000

standardi1ed the language.

Describing a design:

'n VHDL an entity is used to describe a hardware module.

2n entity can be described using, !. 0ntity declaration. /. 2rchitecture. ). (onguration 3. 4ac5age declaration. . 4ac5age body.

Entity declaration:

't denes the names, input output signals and modes of a hardware module.

ynta!:

entityentity6name is

"ortdeclaration7

endentity6name7

2n entity declaration should starts with 8entity9 and ends with 8end9 5eywords.

4orts are interfaces through which an entity can communicate with its environment.

0ach port must have a name, direction and a type. 2n entity may have no portdeclaration also. The direction will be input, output or inout.

:ame of the lab ; 0-(2D&ignature of the er 4ort can be read and written, it can have only one

source.


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't describes the internal description of design or it tells what is there inside

design. 0ach entity has atleast one architecture and an entity can have many

architecture. 2rchitecture can be described using structural, dataow, behavioral or

mied style. 2rchitecture can be used to describe a design at di>erent levels ofabstraction li5e gate level, register transfer level $?TL% or behavior level.

ynta!:

architect#rearchitecture6name o$entity6name

architecture6declarative6part7

begin

&tatements7

endarchitecture6name7

Here we should specify the entity name for which we are writing the

architecture body. The architecture statements should be inside the begin and end

5eyword. 2rchitecture declarative part may contain variables, constants, or

component declaration.

Con%g#ration: 'f an entity contains many architectures and any one of the possible

architecture binding with its entity is done using conguration. 't is used to bind the

architecture body to its entity and a component with an entity.

ynta!:

con%g#rationconguration6name o$entity6name is

bloc56conguration7

end conguration6name.

&loc'(con%g#rationdenes the binding of components in a bloc5. This can be

written as

$orbloc56name

component6binding7

end$or7

&loc'(na)eis the name of the architecture body. (omponent binding binds the

components of the bloc5 to entities. This can be written as,

$orcomponent6labels:component6name

:ame of the lab ; 0-(2D&ignature of the


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bloc56conguration7

end$or7

The internal wor5ing of an entity can be dened using di>erent modelingstyles inside architcture body. They are

*. Dataow modeling.+. *ehavioral modeling.,. &tructural modeling.

tr#ct#re o$ an entity:

Let9s try to understand with the help of one eample.

Data-o. )odeling: 'n this style of modeling, the internal wor5ing of an entity

can be implemented using concurrent signal assignment.

Let9s ta5e half adder eample which is having one @=? gate and a 2:D gate.

Library'0007

#se'000.&TD6L=A'(6!!B3.all7entityha6en is

/ort$2,*:inbit7&,(:o#tbit%7endha6en7architect#reha6ar o$ha6enis



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begin&012 !or*7

(012 and*7

endha6ar7

Here &TD6L=A'(6!!B3 is an '000 standard which denes a nine-value logic

type, called &TD6CL=A'(. use is a 5eyword, which imports all the declarations from

this pac5age. The architecture body consists of concurrent signal assignments,

which describes the functionality of the design. henever there is a change in ?H&,

the epression is evaluated and the value is assigned to LH&.

&eha2ioral )odeling:

'n this style of modeling, the internal wor5ing of an entity can be implemented

using set of statements.'t contains;

4rocess statements

&eEuential statements

&ignal assignment statements

ait statements

4rocess statement is the primary mechanism used to model the behavior of

an entity. 't contains seEuential statements, variable assignment $;F% statements or

signal assignment $GF% statements etc. 't may or may not contain sensitivity list. 'f

there is an event occurs on any of the signals in the sensitivity list, the statements

within the process are eecuted.

'nside the process the eecution of statements will be seEuential and if one

entity is having two processes the eecution of these processes will be concurrent.

2t the end it waits for another event to occur.

library'0007#se'000.&TD6L=A'(6!!B3.all7



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entityha6beha6en is /ort$ 2 :in&IT7 * :in&IT7 & :o#t&IT7 ( :o#t&IT %7endha6beha6en7architect#reha6beha6ar o$ha6beha6enisbegin process6beh:/rocess$2,*% begin &012 !or*7

(012 and*7end/rocessprocess6beh7endha6beha6ar7

Here when ever there is a change in the value of a or b the process statements are

eecuted.

tr#ct#ral )odeling: The implementation of an entity is done through set of

interconnected components. 't contains;

&ignal declaration.

(omponent instances

4ort maps.

ait statements.

Co)/onent declaration;

ynta!: co)/onentcomponent6name isI List6of6interface ports7 endco)/onentcomponent6name7

*efore instantiating the component it should be declared using component

declaration as shown above. (omponent declaration declares the name of the

entity and interface of a component.



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Let9s try to understand this by ta5ing the eample of full adder using / half adder

and ! =? gate.

The program we have written for

half adder in dataow modeling is instantiated as shown above. ha6en is the name

of the entity in dataow modeling. (!, (/, &! are the signals used for internal

connections of the component which are declared using the 5eyword signal. 4ort

map is used to connect di>erent components as well as connect components to

ports of the entity.

(omponent instantiation is done as follows.

Co)/onent(label; component6nameport map$signal6list%7

ignal(listis the architecture signals which we are connecting to component ports.

This can be done in di>erent ways. hat we declared above is positional binding.

=ne more type is the named binding. The above can be written as,

H2!;ha6en port map$2 FJ 2,* FJ *, & FJ &! ,( FJ (! %7

H2/;ha6en port map$2 FJ &!,* FJ (in, &FJ &C+, ( FJ (/%7

Test bench:

The correctness of the above program can be chec5ed by writing the test bench.

The test bench is used for generating stimulus for the entity under test. Let9s write

a simple test bench for full adder.



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Here now isa predened function that returns the current simulation time.

hat we saw upto this is component instantiation by positional and by name.

'n this test bench eample the entity is directly instantiated. The direct entity

instantiation synta is;

(omponent6label;entityentity6name$architecture6name%

port map$signal6list%7



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D 4LI"54LO"

6I7;To design a code for D ip-op using active HDL and verify the responses .

O4TW6RE ;2ctive HDL

CIRCUIT DI68R67 :

"IN DI68R67:

!3 )

!) 3

!/

!! B

!

/

"

!M

!



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"RO8R67 :

Library '000Cse '000.&TD6L=A'(6!!B3.allentity d-> is4ort$ d,cl5;in &TD6L=A'(7 E;out &TD6L=A'(%7end d6>7architecture d6> of d6> isbegin

process$d,cl5%beginif$cl59event and cl5F9!9%thenEGFd7end if7end process7end d6>7

"ROCEDURE :

!. =pen active HDL software and clic5 on Ocreate new leP./. Type the entity name and select the input and output ports.). Type the program and compile without errors.3. &elect the input and output variables and add to waveform.. &imulate by giving appropriate values to the variables.B. ?estart simulation and run the program.. =bserve the output waveform corresponding to the inputs.

TRUTH T6&LE :



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OUT"UT W6VE4OR7:



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REULT :

The design code for D ipop using active HDL software is veried.

95&IT HI4T RE8ITER

6I7 :To design a code for 3-bit shift register using active HDL and verify the

responses on simulator with hardware 5it.

O4TW6RE; 2ctive HDL

CIRCUIT DI68R67;

': N N2 5i N* N(

ND

cl5

"IN DI68R67:



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"RO8R67 :

Library '000Cse '000.&TD6L=A'(6!!B3.all7entity shift3 is4ort$ w,cl5;in &TD6L=A'(7 E;out &TD6L=A'(6V0(T=?$! to 3% %7end shift37architecture shift3 of shift3 issignal sreg;std6logic6vector$! to 3%7begin

process$cl5%beginif $cl59event and cl5F9!9%thensreg$3%GFw7sreg$)%GFsreg$3%7sreg$/%GFsreg$)%7sreg$!%GFsreg$/%7end if7end process7EGFsreg7end shift37

"ROCEDURE :

!. =pen active HDL software and clic5 on Ocreate new leP./. Type the entity name and select the input and output ports.). Type the program and compile without errors.3. &elect the input and output variables and add to waveform.. &imulate by giving appropriate values to the variables.B. ?estart simulation and run the program.



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. =bserve the output waveform corresponding to the inputs.

TRUTH T6&LE:

OUT"UT W6VE4OR7:



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REULT :

The design code for 3 bit shift register using active HDL software isveried.



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"RO8R67:

Library ieee7use ieee.std6logic6!!B3.all7entity S5>! isport $s,r,S,5,cl5;in bit7E;inout bit7En;out bit;F!%7end S5>!7

architecture S5> of S5>! isbeginprocess$s,r,cl5%beginif rFM then EGFM after !Mns7elsif sFM then EGF! after !Mns7elsif cl5FM and cl5 event thenEGF$S and not E% or $not 5 and E% after !Mns7end if7end process7EnGFnot E7end S5>7

"ROCEDURE:


TRUTH T6&LE:



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OUT"UT W6VE4OR7:



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REULT:

The design code for QR ipop using active HDL software is veried.



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9 &IT COUNTER

6I7; To design a code for 3bit counter using active HDL and verify the.

O4TW6RE ; 2ctive HDLCIRCUIT DI68R67:

"IN DI68R67:



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"RO8R67:

Library ieee7use ieee.std6logic6!!B3.all7entity S5>! isport $s,r,S,5,cl5;in bit7E;inout bit7En;out bit;F!%7end S5>!7

architecture S5> of S5>! isbeginprocess$s,r,cl5%beginif rFM then EGFM after !Mns7elsif sFM then EGF! after !Mns7elsif cl5FM and cl5 event thenEGF$S and not E% or $not 5 and E% after !Mns7end if7end process7EnGFnot E7end S5>7

"ROCEDURE:

!. =pen active HDL software and clic5 on Ocreate new leP./. Type the entity name and select the input and output ports.). Type the program and compile without errors.3. &elect the input and output variables and add to waveform.. &imulate by giving appropriate values to the variables.B. ?estart simulation and run the program.. =bserve the output waveform

corresponding to the inputs.

TRUTH T6&LE:



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OUT"UT W6VE4OR7:



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REULT:

The design code for 3bit counter using active HDL software is veried.

= ! * 7ULTI"LE>ER

6I7: To design the codes for # ! multipleer using active HDL software and verify

the response.

O4TW6RE; 2ctive HDL software.

CIRCUIT DI68R67:

"IN DI68R67:



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end mu!7

"ROCEDURE :

!. =pen active HDL software and clic5 on Ocreate new leP.

/. Type the entity name and select the input and output ports.

). Type the program and compile without errors.

3. &elect the input and output variables and add to waveform.

. &imulate by giving appropriate values to the variables.

B. ?estart simulation and run the program.


TRUTH T6&LE :

OUT"UT W6VE4OR7:



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REULT :

The design code for # ! multipleer using active HDL software is

veried.

= ! , ENCODER

6I7; To design the codes for # ) encoder using active HDL software and verify

the response .


CIRCUIT DI68R67:



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"IN DI68R67 :

"RO8R67:

library '0007use '000.std6logic6!!B3.all7



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entity enc is port $ d; in &TD6L=A'(6V0(T=? $ down to M%7 y; out &TD6L=A'(6V0(T=? $/ down to M%%7

end enc7architecture enc of enc isbeginprocess$d%

begin

case d iswhen U!MMMMMMMUFJ yGFUMMMU7when UM!MMMMMMUFJ yGFUMM!U7

when UMM!MMMMMUFJ yGFUM!MU7when UMMM!MMMMUFJ yGFUM!!U7when UMMMM!MMMUFJ yGFU!MMU7when UMMMMM!MMUFJ yGFU!M!U7when UMMMMMM!MUFJ yGFU!!MU7when others FJ yGFU!!!U7end case7end process7end enc7

"ROCEDURE:






B. ?estart simulation and run the program.. =bserve the output waveform corresponding to the inputs.

TRUTH T6&LE:



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LO8IC 86TE

6I7; To design the codes for logic gates using active HDL software and verify the

response .


CIRCUIT DI68R67 :

"IN DI68R67 :



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REULT :

The design code for logic gates using active HDL software is veried.

+>9 DECODER

6I7; To design the code for / 3 decoder using active HDL software and verify the

response.


CIRCUIT DI68R67 :

"IN DI68R67 :



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"RO8R67 :

Library '0007Cse '000.&TD6L=A'(6!!B3.2LL7Cse '000.&TD6L=A'(62?'TH.2LL7

Cse '000.&TD6L=A'(6C:&'A:0D.2LL70ntity decoder is4ort

$ c ; out &TD6L=A'( 7 d ; out &TD6L=A'( 7 e ; out &TD6L=A'( 7 f ; out &TD6L=A'( 7 a ; out &TD6L=A'( 7 b ; out &TD6L=A'( 7 %72rchitecture behaviour of decoder is*egin c GF $not a% and $not b% 7 d GF $not a% and b 7

e GF a and $not b% 7 f GF a and b 70nd decoder 7

"ROCEDURE :



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!. =pen active HDL software and clic5 on Ocreate new leP./. Type the entity name and select the input and output ports.). Type the program and compile without errors.3. &elect the input and output variables and add to waveform.

. &imulate by giving appropriate values to the variables.B. ?estart simulation and run the program.. =bserve the output waveform corresponding to the inputs.

TRUTH T6&LE :

a & C d e $

M M ! M M MM ! M ! M M

! M M M ! M! ! M M M !

OUT"UT W6VE4OR7:



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REULT :

The design code for / 3 decoder using active HDL software is veried.

4ULL 6DDER

6I7; To design a code for


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"RO8R67 :

Library '000 7

use ieee.std6logic6!!B3.all 7

0ntity fulladd is

port $ cin, , y ; in std6logic 7

s, cout ; out std6logic % 7

end fulladd 7

architecture beh of fulladd is

begins GF or y orcin 7

coutGF $ and y% or $cin and % or $cin and y% 7

end beh7

"ROCEDURE :





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. &imulate by giving appropriate values to the variables.B. ?estart simulation and run the program.


TRUTH T6&LE :

OUT"UT W6VE4OR7:



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6I7; To design a code for De-multipleer using active HDL and verify theresponses.

O4TW6RE; 2ctive HDL

CIRCUIT DI68R67:

"IN DI68R67:



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"RO8R67:

library '0007use '000.std6logic6!!B3.all7

entity demu! is

port $

f; in &TD6L=A'(7

s; in &TD6L=A'(6V0(T=? $/ downto M%7

y; out &TD6L=A'(6V0(T=?$ downto M%

%7

end demu!7

architecture demu! of demu! is

begin

y$M% GF f when sFUMMMU else M7

y$!% GF f when sFUMM!U else M7

y$/% GF f when sFUM!MU else M7

y$)% GF f when sFUM!!U else M7

y$3% GF f when sFU!MMU else M7

y$% GF f when sFU!M!U else M7

y$B% GF f when sFU!!MU else M7

y$% GF f when sFU!!!U else M7

end demu!7

"ROCEDURE :


/. Type the entity name and select the input and output ports.). Type the program and compile without errors.



B. ?estart simulation and run the program.




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TRUTH T6&LE :

OUT"UT W6VE4RO7:



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REULT :

The design code for D ipop using active HDL software is veried.

9 &IT &IN6R TO 8R6

6I7; To design a code for 3 bit binary to gray code using active HDL and verify theresponses.

O4TW6RE; 2ctive HDL.

CIRCUIT DI68R67:

"IN DI68R67:



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"RO8R67:

library '0007

use '000.std6logic6!!B3.all7

entity b/g is

port $

b; in &TD6L=A'(6V0(T=? $) downto M%7

g; out &TD6L=A'(6V0(T=? $) downto M%

%7

end b/g7

architecture b/g of b/g is

begin

g$)%GFb$)%7

g$/%GFb$)% or b$/%7

g$!%GFb$/% or b$!%7

g$M%GFb$!% or b$M%7

end b/g7

"ROCEDURE:


TRUTH T6&LE :



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OUT"UT W6VE4OR7:



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REULT :

The design code for 3 bit binary to gray code using active HDL software is veried.

CO7"6R6TOR

6I7;To design a code for D ip-op using active HDL and verify the responses.

CIRCUIT DI68R67 :

"IN DI68R67:



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"RO8R67 :

library '0007

use '000.std6logic6!!B3.all7

entity comparator is

port $

a; in &TD6L=A'(7

b; in &TD6L=A'(7

agtb; out &TD6L=A'(7

altb; out &TD6L=A'(7

aeEb; out &TD6L=A'(

%7end comparator7

architecture comparator of comparator is

begin

aeEbGF ! when a F b else M 7

agtbGF ! when a J b else M 7

altbGF ! when a G b else M 7

end

"ROCEDURE :

!. =pen active HDL software and clic5 on Ocreate new leP./. Type the entity name and select the input and output ports.). Type the program and compile without errors.3. &elect the input and output variables and add to waveform.. &imulate by giving appropriate values to the variables.. =bserve the output waveform corresponding to the inputs.

TRUTH T6&LE :



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OUT"UT W6VE4OR7:



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REULT :

The design code for 3 bit comparator using active HDL software is veried.

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