RESEARCH POSTER PRESENTATION DESIGN © 2015 w ww.PosterPresentations.com • Chip design quality affects the manufacturing process. • Dielectric thickness inside chip during tape-out may degrade yield. • Thickness variation is proportional to local feature density [4] (Fig. 4) • During Chemical-Mechanical Polishing (CMP) process, the thickness variation may increase due to difference in density of overlaying layer. [5]. • To improve chip manufacturing yield, foundries apply some rules. • If the layout doesn’t meet density requirements, foundries will either ask the designers to redesign it or they modify the layout. • They may insert non-functional blocks to improve patterndensity. • A layout needs to be analyzed for its density distribution. I. INTRODUCTION II. Motivation Our proposed density-uniformity-aware analog layout retargeting method is composed of several steps as shown in Fig. 7 and briefly explained as follows: III. METHODOLOGY IV. Experimental Results V. CONCLUSION In this research, we presented our proposed method to improve density uniformity of analog layouts during the layout retargeting process. Unlike other previous works, we take advantage of symbolic template and modify the functional geometries of analog layouts to improve density uniformity. Our proposed method is aimed to reduce performance-degrading effects caused by dummy fill insertion while preserving density uniformity distribution in the layout migration. REFERNCES [1] www.dreamstime.com [2] www.semimd.com/chipworks [3] www.extremetech.com [4] A. B. Kahng, G. Robins, A. Singh, H.Wang, and A. Zelikovsky, "Filling algorithms and analyzes for layout density control," IEEE Trans. Computer-Aided Design, vol. 18, pp. 445-462, Apr, 1999. [5] A. B. Kahng, and K. Samadi, "CMP Fill Synthesis: A Survey of Recent Studies," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 3-19, Jan. 2008. [6] www.jss.ecsdl.org [7] N. Jangkrajarng, S. Bhattacharya, R. Hortono, and C.J. R. Shi, "IPRAIL-Intellectual Property Reuse-based Analog IC Layout Automation," Integration VLSI, vol. 36, no. 4, pp. 237-262, Nov. 2003. ACKNOWLEDGEMENT In CMP a silicon wafer is polished by a pad and using slurry. This may cause some variation in Inter-Layer Dielectric thickness (ILD) which can be reduced by inserting some dummy fills. In CMP a silicon wafer is polished by a pad and using slurry. This may cause some variation in Inter-Layer Dielectric thickness (ILD) which can be reduced by inserting some dummy fills. Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John’s, NL, Canada, A1B 3X5 Gholamreza Shomalnasab, Dr. Lihong Zhang Density-Uniformity-Aware Analog Layout Retargeting Fig.1. A chip Image [1] Fig. 3. SEM image of connections inside a chip [3] Fig. 2. SEM cross-section image of a chip [2] Fig.5. CMP process [6] Fig.6. Reducing the effect of CMP by inserting dummy fills [5] Fig. 9. Interconnect Widening Approach pseudo-code • We convert initial layout to a symbolic template and eventually a constraint graph. • Constraint graph is optimized by graph compaction algorithm to retarget to new design specifications. • We used fixed dissection density analysis method to analyze density distribution in the layout shown in Fig. 8. • We formulate a LP problem to plan for improving density distribution. The pseudo-code and equations are showed in Fig. 9 and Table 1. • The obtained solution from LP solver is implemented in the layout in the form of resizing layout tiles, it is called InterconnectWidening (IW). • As a complementary method, we use dummy fill insertion (DF) to compensate the variations which is not fixed by IW yet. Fig. 8. - A n×n layout is partitioned into smaller cells each of which has (w/r)×(w/r) size. Each w×w window (light gray) consists of r×r cells. A pair of windows from different dissections may overlap. For each density-rule-constrained layer in the layout 1. Split any shared tiles 2. Analyze the density 3. Calculate the interconnect width capacity by calling IWC( ) 4. Solve LP problem 5. For each tile 5.1.Identify recommended solution for the corresponding partition-cell 5.2. Calculate new size based on the given solution 5.3. Change size based on the critical path & available room for expansion 5.4. Do depth-first search to update node rooms in CG 5.5. Update the corresponding arcs in CG 6. Remove extra arcs to unbound inline edges 7. Solve the longest-path problem for the CG Maximize: (M-N) Subject to: 0 ≤ ≤ ܫܥ( ܥ ) , = 0,…, − 1 (1) M ≤ all ݓ ݐݏݏ, ݐ= 0, … , − ݎ+1 (2) N ≥ all ݓ ݐݏݏ, ݐ= 0, … , − ݎ+1 (3) L ≤ all ݓ ݐݏ≤ ݏ, ݐ= 0, … , − ݎ+1 (4) ݓ ݐݏ= ܦ ݐݏ+ݎ−1 ݐ= + +ݎ−1 ݏ= ݐݏ+ݎ−1 ݐ= +ݎ−1 ݏ= (ݏ, ݐ= 0,…, − ݎ+ 1), (5) Table 1. LP Formulation of our proposed method Fig.7. Flow Diagram of our proposed method • Our proposed method is implemented in C++. • IPRAIL [7] is used as the backbone platform. • We implemented a few features (such as IWC guide to LP and tile splitting) in our methodology to improve the results. • The final layout density variation is compared for two test cases, a two- stage opamp and a cascode opamp. • Layout is portioned into 4×4 cells and each sliding window includes 2×2 cells with the step size of one cell. This work was supported in part by the Natural Sciences and Engineering Research Council of Canada (NSERC), Canada Foundation for Innovation (CFI), Research and Development Corporation (RDC) of Newfoundland and Labrador (through its Industrial Research and Innovation Fund, Ocean Industries Student Research Award, and ArcticTECH R&D Award), and Memorial University of Newfoundland. Layouts for test Window Density Variation Number of Fills Aimed window Density Run-time (Sec) Initial Layout IW Layout Final Layout Two-stage Opamp Sole DF 24.95 NA 4.625 32 47.64 0.849 IW-DF Without IWC Guidance 24.95 19.28 1.468 34 45.21 2.737 Without Splitting 24.95 16.25 3.541 40 48.16 2.442 Proposed Method 24.95 12.40 0.068 11 32.1 2.708 Cascode Opamp Sole DF 12.46 NA 0.04 9 23.1 0.688 IW-DF Without IWC Guidance 12.46 10.16 0 8 22.89 2.233 Without Splitting 12.46 8.85 0 16 37.16 2.053 Proposed Method 12.46 6.9011 0 10 23.06 2.269 Table 2. Comparison of density variation of two test layouts Fig. 10. Snap shot of two-stage opamp (top) and cascode opamp (bottom) layouts after applying our proposed method Fig. 4. Oxide thickness and local density relationship [4] Our objective in this research is to improve density uniformity by taking advantage of the special features offered by the analog layouts. Thus, the final generated layout cannot only meet the updated specifications in the new technology, but also sustain high yield with surface planarity. Here, we used analog layout migration to be able to rearrange the input layout. Dummy fills are non functional blocks inserted in the sparse areas of the layout to improve pattern density distribution and consequently, they reduce Dielectric thickness variation. Dummy fills are non functional blocks inserted in the sparse areas of the layout to improve pattern density distribution and consequently, they reduce Dielectric thickness variation.
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RESEARCH POSTER PRESENTATION DESIGN © 2015
www.PosterPresentations.com
• Chip design quality affects the manufacturing process.• Dielectric thickness inside chip during tape-out may degrade yield.• Thickness variation is proportional to local feature density [4] (Fig. 4)• During Chemical-Mechanical Polishing (CMP) process, the thickness
variation may increase due to difference in density of overlaying layer.[5].
• To improve chip manufacturing yield, foundries apply some rules.• If the layout doesn’t meet density requirements, foundries will either ask
the designers to redesign it or they modify the layout.• They may insert non-functional blocks to improve pattern density.• A layout needs to be analyzed for its density distribution.
I. INTRODUCTION
II. Motivation
Our proposed density-uniformity-aware analog layout retargeting method is composed of several steps as shown in Fig. 7 and briefly explained as follows:
III. METHODOLOGY
IV. Experimental Results
V. CONCLUSION In this research, we presented our proposed method to improve densityuniformity of analog layouts during the layout retargeting process. Unlikeother previous works, we take advantage of symbolic template and modifythe functional geometries of analog layouts to improve density uniformity.Our proposed method is aimed to reduce performance-degrading effectscaused by dummy fill insertion while preserving density uniformitydistribution in the layout migration.
REFERNCES
[1] www.dreamstime.com[2] www.semimd.com/chipworks[3] www.extremetech.com[4] A. B. Kahng, G. Robins, A. Singh, H.Wang, and A. Zelikovsky, "Fillingalgorithms and analyzes for layout density control," IEEE Trans.Computer-Aided Design, vol. 18, pp. 445-462, Apr, 1999.[5] A. B. Kahng, and K. Samadi, "CMP Fill Synthesis: A Survey of RecentStudies," IEEE Trans. on Computer-Aided Design of Integrated Circuitsand Systems, vol. 27, no. 1, pp. 3-19, Jan. 2008.[6] www.jss.ecsdl.org[7] N. Jangkrajarng, S. Bhattacharya, R. Hortono, and C.J. R. Shi,"IPRAIL-Intellectual Property Reuse-based Analog IC LayoutAutomation," Integration VLSI, vol. 36, no. 4, pp. 237-262, Nov. 2003.
ACKNOWLEDGEMENT
In CMP a silicon wafer ispolished by a pad andusing slurry. This maycause some variation inInter-Layer Dielectricthickness (ILD) which canbe reduced by insertingsome dummy fills.
In CMP a silicon wafer ispolished by a pad andusing slurry. This maycause some variation inInter-Layer Dielectricthickness (ILD) which canbe reduced by insertingsome dummy fills.
Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John’s, NL, Canada, A1B 3X5Gholamreza Shomalnasab, Dr. Lihong Zhang
Density-Uniformity-Aware Analog Layout Retargeting
Fig.1. A chip Image [1]
Fig. 3. SEM image of connections inside a chip [3]
Fig. 2. SEM cross-section image of a chip [2]
Fig.5. CMP process [6]
Fig.6. Reducing the effect of CMP by inserting dummy fills [5]
Fig. 9. Interconnect Widening Approach pseudo-code
• We convert initial layout to a symbolic template and eventually aconstraint graph.
• Constraint graph is optimized by graph compaction algorithm to retargetto new design specifications.
• We used fixed dissection density analysis method to analyze densitydistribution in the layout shown in Fig. 8.
• We formulate a LP problem to plan for improving density distribution.The pseudo-code and equations are showed in Fig. 9 and Table 1.
• The obtained solution from LP solver is implemented in the layout inthe form of resizing layout tiles, it is called Interconnect Widening (IW).
• As a complementary method, we use dummy fill insertion (DF) tocompensate the variations which is not fixed by IW yet.
Fig. 8. - A n×n layout is partitioned into smaller cells each of which has (w/r)×(w/r) size. Each w×w window (light gray) consists of r×r
cells. A pair of windows from different dissections may overlap.
For each density-rule-constrained layer in the layout1. Split any shared tiles2. Analyze the density3. Calculate the interconnect width capacity by calling IWC( )4. Solve LP problem5. For each tile
5.1.Identify recommended solution for the correspondingpartition-cell5.2. Calculate new size based on the given solution5.3. Change size based on the critical path & availableroom for expansion5.4. Do depth-first search to update node rooms in CG5.5. Update the corresponding arcs in CG
6. Remove extra arcs to unbound inline edges7. Solve the longest-path problem for the CG
Maximize: (M-N) Subject to:0 ≤ 푃푖푗 ≤ 퐼푊퐶(퐶푖푗)푖, 푗 = 0, … , 푛 − 1 (1)
M ≤ all푤푠푡푠,푡 = 0, … ,푛 − 푟 + 1 (2)
N ≥ all푤푠푡푠,푡 = 0, … ,푛 − 푟+ 1 (3)
L ≤ all푤푠푡 ≤ 푈푠, 푡 = 0, … ,푛 − 푟 + 1 (4)
푤푠푡 = 퐷푠푡
푗+푟−1
푡=푗
+푖+푟−1
푠=푖
푃푠푡
푗+푟−1
푡=푗
푖+푟−1
푠=푖(푠, 푡 = 0, … , 푛 − 푟+ 1),
(5)
Table 1. LP Formulation of our proposed method
Fig.7. Flow Diagram of our proposed method
• Our proposed method is implemented in C++.• IPRAIL [7] is used as the backbone platform.• We implemented a few features (such as IWC guide to LP and tile
splitting) in our methodology to improve the results.• The final layout density variation is compared for two test cases, a two-
stage opamp and a cascode opamp.• Layout is portioned into 4×4 cells and each sliding window includes
2×2 cells with the step size of one cell.
This work was supported in part by the Natural Sciences and EngineeringResearch Council of Canada (NSERC), Canada Foundation for Innovation(CFI), Research and Development Corporation (RDC) of Newfoundlandand Labrador (through its Industrial Research and Innovation Fund, OceanIndustries Student Research Award, and ArcticTECH R&D Award), andMemorial University of Newfoundland.
Layouts for testWindow Density Variation
Number of Fills
Aimed window Density
Run-time (Sec)
Initial Layout
IW Layout
Final Layout
Two-
stag
e O
pam
p
Sole DF 24.95 NA 4.625 32 47.64 0.849
IW-D
F
Without IWC Guidance 24.95 19.28 1.468 34 45.21 2.737
Without Splitting 24.95 16.25 3.541 40 48.16 2.442
Proposed Method 24.95 12.40 0.068 11 32.1 2.708
Casc
ode
Opa
mp
Sole DF 12.46 NA 0.04 9 23.1 0.688
IW-D
F Without IWC Guidance 12.46 10.16 0 8 22.89 2.233
Without Splitting 12.46 8.85 0 16 37.16 2.053
Proposed Method 12.46 6.9011 0 10 23.06 2.269
Table 2. Comparison of density variation of two test layouts
Fig. 10. Snap shot of two-stage opamp (top) and cascode opamp(bottom) layouts after applying our proposed method
Fig. 4. Oxide thickness and local density relationship [4]
Our objective in this research is to improve density uniformity by takingadvantage of the special features offered by the analog layouts. Thus, thefinal generated layout cannot only meet the updated specifications in thenew technology, but also sustain high yield with surface planarity.Here, we used analog layout migration to be able to rearrange the input layout.
Dummy fills are nonfunctional blocks insertedin the sparse areas of thelayout to improve patterndensity distribution andconsequently, they reduceDielectric thicknessvariation.
Dummy fills are nonfunctional blocks insertedin the sparse areas of thelayout to improve patterndensity distribution andconsequently, they reduceDielectric thicknessvariation.
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