Results of the ASIC Test New Developments Next Steps Project Meeting.
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DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 2
Results of the ASIC Test
• Delivery Date of ASIC: 14. August 2014
• Delivery Date of Hybrid Board: 27. August 2014
• Start Measurements: 1. September
• Check of all Functionalities
• Timing Fast Trigger
• Slow Trigger of 1. Row
• Readout Hit Matrix
• Using Test Pads
vvvv
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 3
Test Setup
Installation and Preparation of Test Software was done by the summer student Alessio Borgheresi (22.07.-11.09.)
Mainboard
Hybrid-Boardwith Test ASIC
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 4
Loading of the Status Control Register via NI Labview
Possibility for Enabling the individual Pixel to stimulate the Sensors Output
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 5
Timing Test Concept
Trigger
Latch
Reset
FF Out
FF Out Dummy
TestInFF
FF-Dummy
DUT
TestIn
Latch
Trigger
Latch
n∙∆t
td
td
∆tN∙∆t
0.5
1
0
Event histogram of FF Out and FF Out Dummy
Ent
ries
(a.u
.)
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 6
Timing Test Results, randomly activated Pixels
0 50 100 150 200 250 3001.76
1.78
1.8
1.82
1.84
1.86
1.88
1.9
1.92
1.94
measured
simulated
Number of active Pixels
De
lay
Tim
e (
ns
)
VDD = 1.2 VVDD2 = 3.3 V
?
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 7
Timing Test Results, Variation of Supply Voltages
0 50 100 150 200 250 3001.65
1.7
1.75
1.8
1.85
1.9
1.95
2
1,2 V1,2 V simulated1,3 V1,4 V1,1 V
Number of active Pixels
De
lay
Tim
e (
ns
)
0 50 100 150 200 250 3001.76
1.78
1.8
1.82
1.84
1.86
1.88
1.9
1.92
1.94
3,3 V3,3 V simulated3,4 V
Number of active Pixels
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 8
Timing Test Results, Corner Variation (simulated, 1.2 V)
0 50 100 150 200 250 3001.2
1.4
1.6
1.8
2
2.2
2.4
2.6
ff
tt
ss
Number of active Pixels
De
lay
Tim
e (
ns
)
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 9
Timing Test Results, extending Circle
0 2 4 6 8 10 12 141.78
1.8
1.82
1.84
1.86
1.88
1.9
measured
simulated
Radius
De
lay
Tim
e (
ns
)
VDD = 1.2 VVDD2 = 3.3 V
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 10
Timing Test Results, extending Point
0 2 4 6 8 10 121.78
1.8
1.82
1.84
1.86
1.88
1.9
measured
simulated
Radius
De
lay
Tim
e (
ns
)
VDD = 1.2 VVDD2 = 3.3 V
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 11
New Developments
> Timing Improvements in the Front-End Electronics Faster by 250 ps
>Design of global Blocks (Sequencer, Controller and Multiplexer) Digital approach
External Signals: Bunch Clock, System Clock, Start/Select
> Improvements on Slow-Trigger performance Consideration of all process corners via extra Switch
DESY FEC | Project Meeting at MPI/HLL | 1.07.2014 | Page 12
Next Steps
> ASIC + (SiMPI-)Sensor Test
Space for 6x6 mm² Sensor Chip
> Sending ASICs to PacTech
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