Customer Presentation ASIC Features ASIC Pricing Immediate Production HDL Design Flow ASIC Features ASIC Pricing Immediate Production HDL Design Flow ASIC.

Customer PresentationCustomer Presentation

ASIC Features

ASIC Pricing

Immediate

Production HDL

Design Flow

ASIC Features

ASIC Pricing

Immediate

Production HDL

Design Flow

ASIC Replacement FPGAs

ASIC Replacement FPGAs

FPGA Flexibility at ASIC Prices!FPGA Flexibility at ASIC Prices!FPGA Flexibility at ASIC Prices!FPGA Flexibility at ASIC Prices!

Agenda

Spartan Highlights

Advantages vs. Gate Arrays

Spartan Alternative to ASIC Conversions

Spartan Replaces Obsolete Gate Arrays

Spartan FPGAs ReplaceGate Arrays in Production

1995 - FPGAs cannot compete with gate arrays

Older process than ASICs Larger die Not I/O pad limited

1998 - FPGAs compete FPGAs are Fab process

drivers, replace DRAMs Competitive die size with

similar number of I/O

160 I/O 160 I/O

1998Gate array,

0.35u, 100K gatesSpartanXL,

0.35u, 10K gates

Gate Array 0.8u, 10K gates

FPGA 1.0u, 5K gates

1995

160 I/O160 I/O

How are Spartan FPGAs Different?Spartan Matches Gate Array Die Size & Cost

No Compromises: Performance, RAM, Cores, and Low Price

5 Volt -> 0.5/0.35µ XCS05 XCS10 XCS20 XCS30 XCS40

3 Volt -> 0.35/0.25µ XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

System Gates 2K-5K 3K-10K 7K-20K 10K-30K 13K-40K

Logic Cells 238 466 950 1368 1862

Max Logic Gates 3,000 5,000 10,000 13,000 20,000

Flip-Flops 360 616 1120 1536 2016

Max RAM bits 3,200 6,272 12,800 18,432 25,088

Max I/O 80 112 160 192 224

Performance 80MHz 80MHz 80MHz 80MHz 80MHz

Xilinx Spartan Series

* Source: Dataquest

Spartan Features: On-chip SelectRAM™

> 75% ASIC designs need RAM *

SelectRAM advantages: Dual Port Synchronous Higher speed (to 100 MHz)

than RAM compilers More flexible - numerous

distributed small RAMs

Standard Bus Interface ProductsPeripheral Component Interconnect Bus (PCI)Other Standard Bus Products

Digital Signal Processing CorrelatorsFilters Transforms DSP Building Blocks

Spartan Core Advantages: – Pre-verified in silicon – Much lower cost than ASIC cores– Simple distribution and licensing

Communications & Networking ProductsAsynchronous Transfer Mode Forward Error Correction

Base-Level Products Basic Elements Math Functions

RISC CPU Cores8-bit RISC core

Processor Peripherals

UARTsOthers

Spartan Extensive Core Support

High-volume pricing < $3.00*High-volume pricing < $3.00*

* 100K units 84PLCC, -3 speed

Spartan FPGAsDesigned for Low Price

Smallest die of any FPGA with RAM

Focused package offering

Streamlined test process

Optimized production flow

5V Price* 3V Price**

XCS05 $3.95 $3.50 XCS05XL $2.95

XCS10 $5.50 $4.80 XCS10XL $3.95

XCS20 $6.50 $6.50 XCS20XL $5.45

XCS30 $7.95 $7.95 XCS30XL $6.95

XCS40 $19.95 $13.80 XCS40XL $9.90

* 100K units, end 1998 ** 100K units, mid 1999Cheapest pkg, slowest speed Cheapest pkg, slowest speed

NEW

Spartan Price Reductions Thru Technology

Core FunctionXCS30XL

PricePercentage of Device Used

EffectiveFunction Cost

UART $6.95 17% $1.20

16-bit RISC Processor $6.95 36% $2.60

16-bit, 16-tap Symmetrical FIR Filter $6.95 27% $1.90

Reed-Solomon Encoder $6.95 6% $0.45

PCI Interface(in PQ208) $8.25 45% $3.80

Cost Effective CoresReplaces Standard Devices

1998 1999 2000

Spartan

$395*

Pric

e

SpartanXL

$295*

0.35 5LM Spartan-II

$200*

0.5 3LM

2.5 Volt

3.3 Volt

5 Volt

* Prices are per 5K system gates, 100K units, slowest speed, 84-PLCC

0.25 5LM

2002

Spartan-III

$150*

1.8 Volt

0.2

Without Compromises ASIC prices

Increased density & speed

More SelectRAMTM

Added cores

Spartan Cost Reduction Roadmap

Spartan Replaces Low-Density Gate Arrays

Syst

em

Gate

s

50 100 150 200 250 300

120

100

80

60

40

20

10

0I/O’s

S30

S20

S401998

1999

Gate Array TerritoryHigh Density,Low I/O

Spartan FPGAsLow Density,High I/OS10

Spartan II

Spartan I

Gates : I/O Fit

S05

* Manufacturer’s Suggested Resale Price

New Car Purchase --New Car Purchase --ExpectedExpected Costs: Costs: MSRP* $$$HiddenHidden costs: costs: Dealer rebates/ holdbacks..

And And UnexpectedUnexpected costs: costs: Dealer prep, destination

charges, rustproofing ….

“Out-the-Door” Costs are Higher! = $$$

Like Buying a New CarCosts of ASIC Design

Expected Gate Array SpartanNRE Typical range of $15-20K

for low density gate arraysNo NRE

Higher cost ofcores & tools

Cores for ASICs can be upto 10x the cost.Unix based synthesis tools$50-100K

Cores for Spartan typicalrange of $5-10K.Complete design tool kit<$10K

Insert scan andATPG

Scan and ATPG needed bymost ASIC productiondesigns

Spartan is 100% tested atthe factory

Debug testvectors

Debugging Test Bench ismajor time element of ASICdesign

Test vectors not neededfor low density FPGAs.

Spartan Avoids Expected Costs

Item Gate Array SpartanMultiple siliconspins

33-50% of designs need extra spin.Extra spin costs 50% of NRE

ReprogrammableMake mistakes with no costpenalty

ASIC sign-off Perform 5 corner simulation (timing,temp, voltage)Planned for 1-2 weeks, takes 3-5weeksASIC 1st time right methodology

Signoff not needed withFPGAs

Expedite proto& initialproduction

Costs include: Fab hot lot, Risk mask/ wafers Rush assembly Cost range of $10-50K

Prototype is immediatelyavailableInitial production quantitiesready when developmentcomplete

Large $commitment

Big MOQ (20-30K pcs)Big min shipment qty (10-20K pcs)Non-cancellable – purchase all WIP

No MOQ needed for FPGAs

Demanddeclines

Saddled with obsolete stock No stock scrapping riskswith FPGAs

Spartan Avoids Unexpected Costs

Item Gate Array SpartanASIC Leadtimes Production leadtimes ~8-16 wks

2-3 month delay = lost sales, profits

Production leadtimes- 0-4weeks to full production

ASIC Inventory Higher levels of stock thanFPGAsHigh carrying costsTies up cash, reduced credit

Low stock, rely on JIT deliveryStock at Disti locationsCash & credit remain available

Design change inproduction

May obsolete stockPurchase customized wafers(WIP)Missed customer shipmentsTakes engineers off newprojects

Easy change to prototype &production.No stock risk or missedshipments

Supply ChainManagement

“Custom” product more difficultJIT

“Standard” product.Off-the-shelf availability

Spartan Avoids Hidden Costs

Gate Array Cost Worksheet - New Designs

* Assumption: Engineering cost @ $10K man/mo

Gate Array Cost* Typical RangeCustomer Costs FPGA

Expected costs:NRE cost $15-20K ______________ NoneATPG from outside service/insert scan 10-20K ______________ NoneHigher cost of ASIC cores 50-150K ______________ 50-70% lessGenerate & debug testbench 10-20K ______________ None

Unexpected costs:Silicon design iteration

(needed in 33-50% of ASIC designs) 15-20K ______________ NoneExtensive customer sign-off (temp, V, MHz sim) 10-20K ______________ NoneExpedite prototype/production

(hot lot, risk mask, rush assembly) 10-40K ______________ NoneLarge $ commitment

(MOQ, min ship qty, ties up cash) 50K+ ______________ NoneDemand slackens (obsolete stock) 10-20K ______________ None

Hidden costs:ASIC production leadtimes (8-10 wks;

lost sales, delayed market entry) 25K+ ______________ NoneDesign change needed in production 20K ______________ NoneScrap obsolete inventory 20-30K ______________ NoneConversion to ASIC costs/risks 20K+ ______________ NoneLarge ASIC inventory-carrying cost 5-15K ______________ NoneStock multiple ASIC codes:

(FPGA single bin stocking) 15-20K ______________ NoneDifficult JIT delivery/supply chain management 10K+ ______________ None

Total Gate Array Costs - New Designs $50K-150K ______________ None

1985 1990 1995Year

1980

DesignProductivity

2000

TransistorsTransistors

Verilog , VHDLVerilog , VHDL

GatesGates

TransistorsTransistors

GatesGates

Behavioral & IPBehavioral & IPBehavioral & IPBehavioral & IP

ASIC Methodology

FPGAMethodology

Schematic

Boolean equations

Verilog , VHDLVerilog , VHDL

RTL

Gap

FPGAs close the design gap

Converging Methodologies

ASIC vendorPlace & Route

ASIC vendorPlace & Route

ASIC

VHDL/VerilogVHDL/Verilog

SynthesisSynthesis

SimulationSimulation

Static timing Static timing

Fab prototype4 wk Lead-time

Fab prototype4 wk Lead-time

Sign-offSign-off

Functional simulation

Functional simulation

Insert ScanInsert Scan

Createtest vectors

Createtest vectors

ECO

VolumeProduction

VolumeProduction

FPGA flow is similar, but:

•SCAN /test vectors not

needed for low densities•Built-in JTAG•Make mistakes, no penalty•Concurrent engineering•Real-time verification

Not needed

with FPGAs

Initial production8-10 wk Lead-time

Initial production8-10 wk Lead-time

Customer quote: “FPGAs – I love being able to make mistakes. I can relax and I don’t have to simulate as much. It’s in my control.

ASICs – We sweat and don’t sleep much until the ASIC is available and tested.” ”

Customer quote: “FPGAs – I love being able to make mistakes. I can relax and I don’t have to simulate as much. It’s in my control.

ASICs – We sweat and don’t sleep much until the ASIC is available and tested.” ”

Gate Array Design Flow

Vendor Simulation Synthesis Schematic Other

Synopsys VSSVital Sim Models

FPGA ExpressFPGA Compiler IIDesign Compiler

DesignWareMotive static timing

Cadence Verilog XL Synergy Concept

Mentor MTI ModelSim V-System

Falcon Framework

Viewlogic Viewsim WorkView

Spartan SupportsGate Array Tools

Synopsys, Cadence, Mentor, Viewlogic 93% of gate array designers use Synopsys

Support of industry standards EDIF, VITAL, VHDL, Verilog, SDF

Spartan Replaces Gate Arrays Up to 40K system gates, 224 I/O

Spartan Meets ASIC Requirements Performance to 80MHz On-chip RAM Silicon-verified Cores Aggressive volume prices

Spartan FPGAs Avoid ASIC Costs Expected costs: NRE, scan, test vectors, …. Hidden costs: Leadtimes, inventory design changes, … Unexpected costs: Spins, sign-off, expediting, ..

HDL Design Flow with Broad 3rd Party Support Synopsys, Cadence, Mentor, MTI, Synplicity, Exemplar , ….

Spartan FPGA Highlights

ASICFPGA

FPGA-to-ASIC Conversion

Direct Translation or Retarget: Engineering costs, Conversion/ NRE fees, 4 month leadtime-to-production, design risks

Spartan FPGA into Production

No added engineering effort, no NREs, Cost reductions through Spartan II, III, ….Full production NOW!

New New ParadigmParadigm

CostlyCostlyPathPath

FPGA Cost-Reduction Paths

Advantages of FPGAs Advantages of FPGAs in Productionin Production

ASIC NRE/ Conversion fees Typical range of $5-25K

Customer engineering costs: Verify new gate array design Simulation, test program, sign-off Characterize/ qualify new prototypes Delay work on next project

Lead-times for conversion-to-production a best case of 4 months

Conversion time 3 weeks, proto 3 weeks, production 10 weeks = 4 months

What is the product life? Is there a mid-life update?

Spartan Avoids ASIC Migration Costs & Lead-times

Any mistake will exist in final ASIC

Design relies on FPGAfeatures

Features not found on ASIC Example: JTAG, on-chip RAM,

global reset, LogiCORE,...

Netlist is modified Often must be modified to add functions

Buffers and clocks are adjusted to optimize drive capability

Timing issues Asynchronous timing Gated clocks

Porting CORES Timing changes between ASIC/FPGA

Complex licensing issues Xilinx / Alliance cores are not

transferable

Risk Result

Spartan AdvantageNo Unexpected Re-design Risks

Gate Array Cost Worksheet - FPGA-to-ASIC Conversion

* Assumption: Engineering cost @ $10K man/mo

FPGA Conversion Costs* Potential Impact Actual FPGA Costs

Expected costs:NRE/conversion fees $15-30K ______________ NoneVerify re-design (sim, vectors, & prototypes) Engineer’s time ______________ NoneInsert JTAG Engineer’s time ______________ NoneHigher cost of ASIC cores 50-150K ______________ 50-70% less

Unexpected costs:4 months conversion-to-production time Higher volume ______________ None

Conversion - 3 weeks needed toPrototype - 3 weeks break evenProduction delivery - 10 weeksTotal time = 16 weeks

Hidden costs:Lose reprogrammability advantage More costly changes/

No field updates ______________ NoneScrap obsolete inventory if design changes 20K ______________ NoneHigher inventory costs/levels 10K ______________ None

Conversion re-design risks:Converting FPGA features

(RAM, JTAG, reset) Not work in-system ______________ NoneModify netlist - new buffers/

new drive capability Not work in-system ______________ NoneDevice timing changes Not work in-system ______________ NonePorting of FPGA Cores Difficult licensing ______________ None

Total ASIC Costs/Impact - Conversions $50K-100K+ ______________ None

New paradigm - Spartan FPGAs in production Spartan proto to production retains FPGA flexibility Faster, less costly transition to volume production

Cost reduction path with future Spartan Series Spartan II in 1999 Spartan III TBA

Spartan avoids redesign costs to gate array Conversion fees Added customer engineering Long-lead-times for production

Eliminates unexpected migration design risks FPGA features difficult to emulate Net list changes

FPGA-to-ASIC ConversionThe New Paradigm: FPGAs in Production

Exited Gate Array in 1996,Exited Gate Array in 1996,FPGA in 1998FPGA in 1998

No new Gate No new Gate Array since 1995 Array since 1995

HDC Series (1.0)H4C Series (0.8H4CPlus Series (0.65)H4EPlus Series (0.65)M5C Series (0.5)

LL7000 Series (2.0 to 10K gates)LL8000 Series (2.0)LCA 10000 Compacted Array (to 50K gates)

Leading Suppliers Exit Gate Arrays

Deep sub-micron process increases mask and wafer costs

Accelerates pace to shut down older processes

LSI & Motorola obsolete Gate Array families

MemecResponsibility

MemecResponsibility

•Specifications•Design files•Timing Diagrams•Package Rqmts.•Quality Stds.•Operating Cond.•Interface Rqmts.•Quantity•Schedule

•Review RFQ Pkg. Business Technical•Prepare Quote: Price Delivery Design Reviews Terms Deliverables Responsibilities

•Create Design•Simulate •Debug•Modify•Test Vectors•Documentation

•Verify Design•Verify Functionality•System Test•System Debug•Verify Test Vectors

Contract

•Materials from: Insight Memec ICG

QuotePackage Design Validation ProductionProduction

CustomerResponsibility

CustomerResponsibility

RFQRFQPackagePackage

Source: Memec Design Services

Example FlowConverting Obsolete ASICs to an FPGA

Leading suppliers exit gate arrays Increasing gate array costs LSI Logic and Motorola

Spartan provides low-cost production solution Add/delete features, integrate logic Update design files to Verilog or VHDL for maintainability Long term stable supply No mask charges

Xilinx Certified Design Centers have conversion experience Design centers can provide turnkey service Insight - Memec Design Services Avnet - Design Services

Obsolete ASIC to Spartan FPGA “Made Easy”

Spartan meets ASIC requirements ASIC features, pre-verified COREs, aggressive prices, avoids costs

of ASIC design and enables flexible production

Supports HDL tools and methodology Broad 3rd party support, flexible design-flow

Provides effective production cost-reduction path

Avoids costs and risks of redesign to gate array

Obsolete gate arrays convert to Spartan FPGAs Majors exit gate arrays Conversion to Spartan made easy by Xilinx Design Centers

Spartan FPGAs Displace Spartan FPGAs Displace Gate Arrays In Production Gate Arrays In Production

ASIC Tools

ASIC design tool:

Synopsys Design Compiler Synopsys HDL synthesis

(93% of designs) VHDL/ Verilog = 50% shares

Synopsys Test Compiler Scan insertion Generate test vectors Increases die size/ impacts

performance

ASIC Tools

ASIC design tool:

Synopsys Design Compiler Synopsys HDL synthesis

(93% of designs) VHDL/ Verilog = 50% shares

Synopsys Test Compiler Scan insertion Generate test vectors Increases die size/ impacts

performance

Spartan Tools

FPGA Alternative:

Synopsys FPGA Express

& FPGA Compiler II

Synplicity, Exemplar New scripts needed

Test Compiler Not Needed Scan is not needed by FPGA 100% factory tested Test vectors are optional

Spartan Tools

FPGA Alternative:

Synopsys FPGA Express

& FPGA Compiler II

Synplicity, Exemplar New scripts needed

Test Compiler Not Needed Scan is not needed by FPGA 100% factory tested Test vectors are optional

Spartan Tool Alternatives

ASIC ToolsASIC design tool:

RAM compiler Expands used gates Lower performance RAM

HDL simulators Cadence VerilogXL MTI, more….

Static timing Quad Motive Synopsys Primetime

Cores In-house 3rd Party

ASIC ToolsASIC design tool:

RAM compiler Expands used gates Lower performance RAM

HDL simulators Cadence VerilogXL MTI, more….

Static timing Quad Motive Synopsys Primetime

Cores In-house 3rd Party

Spartan ToolsFPGA Alternative:Xilinx compiler On-chip SelectRAM No performance impact

HDL simulators Cadence VerilogXL MTI, more …..

Static timing Quad Tier 1 in Alliance 2.1 Xilinx Static Timing Cores LogiCORE AllianceCORE

Spartan ToolsFPGA Alternative:Xilinx compiler On-chip SelectRAM No performance impact

HDL simulators Cadence VerilogXL MTI, more …..

Static timing Quad Tier 1 in Alliance 2.1 Xilinx Static Timing Cores LogiCORE AllianceCORE

Spartan Tool Alternatives

FPGA design optimization requires architectural “know-

how”– Complex functions operate > 50MHz – Critical design technique is pipelining

FPGA design optimization requires architectural “know-

how”– Complex functions operate > 50MHz – Critical design technique is pipelining

There Are Design There Are Design Methodology DifferencesMethodology Differences

HDLs were developed for ASICs Achieving 66MHz speed with ASIC is easy FPGAs require more structured techniques

HDLs were developed for ASICs Achieving 66MHz speed with ASIC is easy FPGAs require more structured techniques

FPGA offer freedom to do design, not under gun till working parts

FPGA offer freedom to do design, not under gun till working parts

Communications & Networking Products Asynchronous Transfer Mode CRC10 Generator and Verifier (CC-130)CRC32 Generator and Verifier (CC-131)Forward Error Correction Reed-Solomon DecoderReed-Solomon EncoderViterbi DecoderBase-Level Products Basic Elements ConstantTwo Input MultiplexerThree Input MultiplexerMath Functions 1's and 2's ComplementAccumulatorScaled by 1/2 AccumulatorRegistered AdderRegistered Loadable AdderRegistered Scaled AdderUARTs XF-8250 Asynchronous Communications ElementM16450 Universal Asynchronous Receiver/TransmitterProcessor Peripherals C2910a Microprogram ControllerM8254 Programmable TimerM8255 Programmable Peripheral Interface

Extensive Core Support for SpartanExtensive Core Support for Spartan

Peripheral Component Interconnect Bus (PCI)PCI32 Spartan Master & Slave InterfacesOther Standard Bus Products IICDigital Signal Processing CorrelatorsOne Dimensional RAM Based CorrelatorOne Dimensional ROM Based CorrelatorFilters Comb Filter16-Tap, 8-Bit FIR FilterSerial Distributed Arithmetic FIR FilterDual Channel Serial Distributor Arithmetic FIR Filter

Parallel Distributed Arithmetic FIR FilterTransforms DFT Core, (Real Data In, Complex Data Out)FFT Core, (1024 Points)DSP Building Blocks SDA FIR Control LogicSine/CosineProcessor Products RISC CPU Cores

Partial list of Spartan Cores

Design: Spartan Gate Array Test vectors/ ATPG None Long Prototyping time Hours Weeks Silicon design change Hours Weeks Cost of iterations None High Cost of CORES Low High

Production: Fast production ramp Excellent Poor

Lead-times Excellent Poor JIT delivery Excellent Poor React to mkt changes Excellent Poor Min order quantities Low High

Inventory: Cost of scrap inventory None High Carrying costs Low High

Spartan FPGA Comparison vs. Gate Arrays

In Design: Eliminates NRE Immediate prototypes No test vectors/ ATPG needed (100% factory tested)

No penalty for design spins with reprogrammability

Broad and verified portfolio of COREs

In Production: Fast time-to-volume production with “off the shelf”

availability Immediate market penetration Facilitates JIT delivery No scrapping inventory Enables field product updates

FPGA Flexibility at ASIC pricesFPGA Flexibility at ASIC prices

Spartan Advantages Summary

ASIC Replacement FPGAs

ASIC Replacement FPGAs

FPGA Flexibility at ASIC Prices!FPGA Flexibility at ASIC Prices!FPGA Flexibility at ASIC Prices!FPGA Flexibility at ASIC Prices!

ASIC Features

ASIC Pricing

Immediate

Production HDL

Design Flow

ASIC Features

ASIC Pricing

Immediate

Production HDL

Design Flow