Development of SOI pixel sensor
28 Sep., 2006
Hirokazu Ishino
(Tokyo Institute of Technology)
for SOIPIX group
Outline
• Motivation• Introduction to the SOI detector • performance of the SOI pixel TEG• summary and plan
SOIPIX collaborators
KEK Detector Technology Project : [SOIPIX KEK Detector Technology Project : [SOIPIX
Group]Group]
Y. Arai(*)Y. Arai(*) 、、 Y. IkegamiY. Ikegami 、、 Y. UshirodaY. Ushiroda 、、Y. UnnoY. Unno 、、 O. TajimaO. Tajima 、、 T. TsuboyamaT. Tsuboyama 、、S. TeradaS. Terada 、、 M. HazumiM. Hazumi 、、 H. IkedaH. IkedaAA 、、K. HaraK. HaraBB 、、 H. IshinoH. IshinoCC 、、 T. KawasakiT. KawasakiDD 、、 H. H.
MiyakeMiyakeEE
Gary VarnerGary VarnerFF, Elena Martin, Elena MartinFF, Hiro Tajima, Hiro TajimaGG,,
M. OhnoM. OhnoHH, K. Fukuda, K. FukudaHH, H. Komatsubara, H. KomatsubaraHH, J. , J.
IdaIdaHH
KEKKEK 、、 JAXAJAXAAA 、、 U. TsukubaU. TsukubaBB 、、 TITTITCC 、、Niigata U.Niigata U.DD 、、 Osaka U.Osaka U.EE, U. Hawaii, U. HawaiiFF, SLAC, SLACGG, ,
OKI Elec. Ind. Co.OKI Elec. Ind. Co.HH
Motivation
• Vertex detectors play an essential role in particle physics– precise decay position measurements of the
heavy quarks and leptons• Silicon On Insulator (SOI) is one of the techniques
usable for future high energy experiments.– radiation hard
• no parasitic NPNP structure, therefore no latch-ups.
• thin active transistor, insensitive to SEU– can be a pixel detector w/o bump bonding– high-resistive handle wafer for radiation
detection
SOI detector design
++++++
−−−−−−
Overview of our SOI detector
• Fully-Depleted CMOS SOI fabricated by OKI Electric Industry Co. Ltd.– commercial technology with 150nm rule– thin Si layer (~20nm) + metal gate
• OKI adopts Unibond wafers from SOITEC, France– Top Si: Cz, ~18Ωcm, p-type, ~40nm thickness– Buried Oxide (BOX): 200nm thickness– handle wafer: Cz, high-resistive with > 1kΩ
• no type assignment, however, identified by I-V measurements, shown later.
• original thickness 650m, thinned to 350m and plated with Al (200nm).
SOI wafer production (UNIBONDTM, SOITEC)
SOI pixel process step flow
Handling wafer
p+n+
Handling wafer
Box
SOI
650um
① After Gate stack formation
② Box Window photo lithography and etching
③ Source/Drain Implantation followed by S/D annealing and Salicidation
Handling wafer
Handling wafer
④ 1st ILD (interlayer dielectrics) filling and CMP planarization
SOI pixel process step flow
Handling wafer
⑤ Contact etching
Handling wafer
⑥ Contact plug filling and 1st Metal formation
650um
Al
p+n+ 250~350um
⑦ 3 ~ 5Metal formation followed by Backside polishing and Al coating
Handling wafer
Diode TEG
Metal contact & p+ implant
Al
I-V characteristics of the handle wafer
substrate is N-type ~700Ωcm ~61012 cm-3
BIAS (V)BIAS (V)
|Cu
rren
t (A
)|
n+ - BACK
P+ - BACK
SOI TEG submitted in 2005
• 2.5 x 2.5 mm2 Chips– Transistor
• p-MOS and n-MOS transistors of different parameters• the characteristics are measured• radiation test has been performed
– Circuit • preamp, Q2T etc.
– Strip • Silicon strip sensor for studying its basic performance
– pixel• 32 x 32 matrix of 20 x 20 m2 pixels• correlated double sample circuit
– reset -> integrate -> readout
Pixel TEG
6" MPW wafer
2.5 mm (chip)
20 m(pixel)
Pixel TEG
CMOS Active Pixel Sensor Type
20 m x 20 m
32 x 32 pixels
Pixel layout
Window for Light Illumination(5.4 x 5.4 um2)
p+ junction
Storage Capacitance(100 fF)
Pixel IV character
Vbreak ~ 100 V
I = 40 A, T = 1 min corner of the bias ring
Smooth the corner and move the ring inward at next submission.
Vback(V)
Iback
(A
)
Hot Spot observed with infrared camera
Pixel detector image
Plastic Mask
Laser (670 nm)Vdet = 10 V
Exposure Time = 7 s
Vdet = 10 V
Wdepletion ~ 44 m
Q ~ 3500 e (0.6 fC)
Expected signal
amplitude was
observed for -
ray.
Pixel detector signal of rays from 90Sr
Vsense Q
C
0.6 fC
8 fF70mV
Back gate effect
Back gate Bias (V)
Th
resh
old
Volt
age (
V)
Back Gate
Signal disappears at 16VConsistent with SPICE simulation.
Bulk: n- (~6 x 1012 cm-3)
BOX (200 nm)
NMOS
(5 m wide p+, 1 x 1020 cm-3)
D = (80, 5, 2 m)
Backbias (0-100 V)
350m
Back gate effect simulation
The p+ implant near the NMOS can
reduces the back gate effect.
ENEXSS : 3D TCAD Simulator
Summary and Plan
• We have started R&D of the SOI pixel detector with OKI Elec. Ind.Co.
• A pixel detector with a 32 x 32 matrix of 20 x 20 m2 pixels has been fabricated and tested.– Photo images are taken successfully– beta rays are successfully detected.
• Back gate effect can be removed by placing p+ implant near the transistors.– the distance and shape are being optimized
using ENEXSS 3D TCAD simulator
• We will submit next TEG on Dec.
backup
Contact & Sheet
Resistance
[Sheet R]
n+ : 33 /square
p+ : 136 /square
[Contact]
(0.16x0.16um2)
n+ : 87 p+ : 218
Hi-R (> 1k cm)
Std. wafer (p+, ~13 cm)
Std. wafer(p+, ~13 cm)
Hi-R (> 1k cm)
p+ contact
n+ contact