International Journal of Computer Information Systems,
Vol. 3 , No. 2, 2011
Design of High Performance AMBA AHB
Reconfigurable Arbiter on system- on- chip
Vimlesh Sahu1 Dr. Ravi Shankar Mishra2 Puran Gour3 M.Tech NIIST BHOPAL HOD (EC) NIIST BHOPAL ASST.Prof.NIIST Bhopal
[email protected] [email protected] [email protected]
Abstract: On chip bus archicture becomes the major
integration method for implementing a SOC (system On
Chip). The effectiveness of a system to resolve,its ability
to logical assignment of the chance to transmit data
width of the data, response to the interrupts etc. The
purpose of this paper is to propose the scheme to
implement such a system using the specification of
AMBA bus protocol .The scheme involves the typical
AMBA features of „single clock edge transition „, Split
transaction “several bus masters” „burst transfer ‟.The
bus arbiter ensures that only one bus master at a time
is allowed to initiate data transfers. Even though the
arbitration protocol is fixed, any arbitration algorithm,
such as highest priority or fair access can be
implemented depending on the application requirements
.The design architecture is written using VHDL(Very
High Speed Integrated Circuits Hardware Description
Language) code using Xilinx ISE Tools .The architecture
is modeled and synthesized using RTL(Register Transfer
Level) abstraction and Implemented on Virtex2 series.
The reconfigurable arbiter can be custom-tuned to
obtain high bandwidth utilization, low latency, and
power effective for on-chip bus communication.
Keywords : Arbiter, Round Robin, Split Transfer, System-
on chip, AMBA, VHDL
Fig:1 AHB ARBITER
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International Journal of Computer Information Systems,
Vol. 3 , No. 2, 2011
1. Introduction
The Advanced Microcontroller Bus Architecture (AMBA)
is an open System-on-Chip bus protocol for high-
performance buses on low-power devices. The AHB is a
pipelined system backbone bus, designed for high-
performance operation. It can support up to 16 bus masters
and slaves that can delay or retry on transfers. It consists of
masters, slaves, an arbiter and an address decoder. It
supports burst and split transfers. The address bus can be up
to 32 bits wide, and the data buses can be up to 128 bits
wide.Arbitration to choose the next bus master uses a round
robin arbitration algorithm. This ensures that no master gets
starved. When a master has locked the bus, the round robin
arbitration is overridden and the master with the lock retains
highest priority to the bus. The sixteen AMBA BUS master0
through Master
Slave 0 through slave 15 are the sixteen AMBA Bus slaves.
The AMBA AHB Bus Arbiter/Decoder contains a default
master-master (), and a default slave –slave().
AMBA AHB Bus Arbiter features are summarized
1. AMBA AHB Bus arbiter function
2. Round robin arbitration
3. Default master-master ()
4. Default slave- slave ()
5.
The arbiter Block monitors the AMBA Bus for request and
chooses the master with highest priority request as the next
AMBA bus transaction master. If there are no request, the
Default Master is chosen as the master to drive the next
AMBA Bus transaction.
The arbiter block monitors the AMBA Bus for request and
chooses the master with highest priority request as the next
AMBA bus transaction master to drive the next AMBA Bus
transaction.
2. The BUS Specification
AHB (AMBA High-performance Bus) is a bus protocol
introduced in AMBA specification version 2 published by
ARM limited Company. In addition to previous release, it
has the following features:
Single edge clock protocol
Split transaction
Several BUS Master
Burst transfers
Pipelined operations
Single cycle bus master handover
Non-tristate implementation
Large bus-widths (64/128 bit)
A simple transaction on the AHB Consist of an address
phase and a subsequent data phase (without wait states: only
two bus –cycles), Access to the target device is controlled
through a MUX (nontristate), There by admitting bus –
access to one bus master access at a time
The AMBA on- chip bus is an established, open
specification that serves as a framework for System on- chip
(SOC) designs. AMBA 2 comprises two system buses: the
Advanced High performance bus (AHB) and the Advance
peripheral Bus (APB). As increasing numbers of companies
adopt AMBA, it is rapidly emerging as a de-facto Standards
for SOC construction and intellectual property (IP) library
development, AMBA provides the “digital glue” that binds
IP core together and is a Key enabler of IP reuse The AHB
ARBITER IP can be broken into subsystem. The two major
components of the system under design are the controller
and data path.
Architectural arbiter Diagram:
3. Data Path
The Data Path Are further divided into several subsystem
blocks, few of them are controlled by controller.Following
are different data path with different functionality.
1. Priority logic block: The priority storage block is
implemented through FSM approach. The priority scheme
follows the round robin theorem of priority. The bus request
have highest priority will get Grant First and Rest of request
will wait for there priority.
Fig 2 Backbone of Arbiter
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International Journal of Computer Information Systems,
Vol. 3 , No. 2, 2011
2. Priority Storage block: The priority storage block is
responsible to store the priority level. IT is the block which
is responsible to enable the Bus req. Block and Interface
Block. Grants are the input pin of this block.
3. Mux arrangement for grant and bus request: 16:1 MUX
for both grant and request.
4. OR gate: This block contains two sets of OR gate, each
set contains 16 OR gate. First OR gate set is used to OR the
output of each individual priority logic block ,second one is
used to OR the individual grant from each priority logic.
5. Counter
6. D-flip-flop
4. Design Description
The following are the major steps involves in the Arbiter
Designs form architectural or functional point of view.
1.The bus request of different master has to pass through the
bus req. block. Which is responsible to Pass the request to
other logical blocks this block is depends upon the enable3
pin which is coming from priority storage block.
2. Bus req. further pass through interface block and goes to
priority logical block. The interface block is giving the
enable signal; to priority logical block and interface block is
responsible for monitor the data transaction through data_
done signal, it can assert and dessert the enable pin depends
upon the data done.
3. This bus_ req. goes to the priority logic block, this block
further decides that which master request will get the
highest priority depending upon the priority this block is
generate the grant signal.
4. This grant signal goes to priority storage block, encoder
block and as output port to interact with Master. After
getting the grant signal Master will send Address, Burst to
indicate the type of transfer, and slave will also send
Hready, Hresp and Hsplit.
5. At the same time when master samples the signal to the
Arbiter Grant signals which are the output of the Arbiter
pass through the mux, inside the Arbiter, for this mux bus _
master no is select line, which indicates that which master is
accessing the bus.
6. The output mux then passes to the controller block which
will generate the necessary signals for counter, i.e. the
controller will control the operation of counter.
7. The grant output from the priority logic block is OR and
then sent to the priority storage block which will store the
priority and pass the enable signal; to the next priority
Depending upon the grant value and the whole operation
is repeated depends upon the transaction
5. Results and Simulation
Fig:3 Simulation window 1
Fig: 4 Simulation window 2
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International Journal of Computer Information Systems,
Vol. 3 , No. 2, 2011
Here the graph is plotted which shows the average number
of CPU bus requests (x-axis) against REQUEST_RATE (y-
axis) values of 50, 40, 30, 20, 15, 10, 5 for three different
cases (a request counter must be kept for each CPU that is
incremented each time the CPU makes a request. The
average number of requests is total # of requests divided by
the number of CPUs):
1.ROUND_ROBIN=TRUE, OVERLAP_GRANT = TRUE
2.ROUND_ROBIN=FALSE, OVERLAP_GRANT = TRUE
3.ROUND_ROBIN=TRUE, OVERLAP_GRANT = FALSE
All three cases should be plotted on the same graph for
comparison purposes.
Waiting time for arbiter in round robin arbitration
algorithm
Device utilization summary:
Selected Device:2v500fg256
Table:1
Number of slices 1566
Number of slice Flip-Flop 535
Number of 4 input LUTs 2750
Number of bonded IOBs 64
Total equivalent gate count for design: 20,095
Power summary: I(mA) P(mW)
------------------------------------------------------
Total estimated power consumption: 348
Vccint 1.50V: 10 15
Vccaux 3.30V: 100 33
Vcco33 3.30V: 1 3
Waiting time for first come first serve arbitration algorithm
Fig:4 Average waiting time
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International Journal of Computer Information Systems,
Vol. 3 , No. 2, 2011
RTL Description
Conclusion:
The design is simulated on Modelsim & verified through
effective test bench. The RTL is implemented on vertex2
(XC2V80, CS144 package) The advantage of this design is
that we have taken care of latch formation, as it is a FPGA
implementation hence with less latch & maximum flip-flop
have enhanced our area efficiency. Cyclic FSM (grey
encoding) has been done for controller design & we
controlled power Consumption .the design can further be
optimized for ASIC design.The Reconfigurable arbiter to
obtain the optimal condition under different system
workloads. The reconfigurable arbiter can be custom-tuned
to obtain high bandwidth utilization, low latency, and power
effective for on-chip bus communication .the architecture–
level power estimation that provides a fast evaluation of the
energy impact of various optimizations early in the design
cycle is essential.
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