Cadence Tool Cadence Tool –– VirtuosoVirtuoso
林冠宇、游雲超
1
林冠宇、游雲超
Advanced Reliable Systems(ARES) Lab.
原作:賴駿凱
Prepare Files (Work Station)
� Linux platform� source /APP/cshbank/icfb.csh
� Technology File� TSMC 0.18um Process:
� 0.18um_Virtuoso4.4.tf
Advanced Reliable
Systems (ARES) Lab.2
� display.drf
� …/vlsi/TSMC018/Virtuoso
� Library File� cds.lib
� Terminal指定資料夾並key in: icfb&
� CIW
初始視窗初始視窗初始視窗初始視窗(1)(1)(1)(1)
Advanced Reliable
Systems (ARES) Lab.3
下skill command處 提示動作 提示mouse key功能
� CIW MENUS
初始視窗初始視窗初始視窗初始視窗(2)(2)(2)(2)
建立新的Library或Cell View將檔案轉入將檔案轉出
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Systems (ARES) Lab.4
� Library Manager
初始視窗初始視窗初始視窗初始視窗(3)(3)(3)(3)
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Systems (ARES) Lab.5
� Library Manager Menus
初始視窗初始視窗初始視窗初始視窗(4)(4)(4)(4)
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Systems (ARES) Lab.6
� File � New � Library
Create Library, Cell (1/3)
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Systems (ARES) Lab.7
Create Library, Cell (2/3)
在Name輸入library名稱(ex:hw1),點選OK
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Systems (ARES) Lab.8
� Compiler a new library with 0.18 technology file
鍵入018ms.tf,點選OK
Create Library, Cell (3/3)
� File � New � Cellview
點選Library Name
輸入Cell Name (ex:inv)
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Systems (ARES) Lab.9
� 點選OK,開啟layout editor畫面
Tool 改選Virtuoso
Layout Editor
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Systems (ARES) Lab.10
Layout Selection Window (LSW)
目前所選之層
Library Name
所有層均show 於layout cellview中
除目前所選之層外在layout cellview中均
不顯示
LSW上所有層在layoutcellview中均可使用
除目前所選之層外在layoutcellview中均
設show於LSW上之層
設LSW上所選層顏色等
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Systems (ARES) Lab.11
不顯示cellview中均不可使用
Layout Editor Menus
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Systems (ARES) Lab.12
Layout Editor Environment Setup(1/2)
� Options � Display
X Snap Spacing :X 軸移動的最小間距
set grid 顯示方式
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Systems (ARES) Lab.13
X 軸移動的最小間距(建議設為0.005)
Value Region:0~32
Layout Editor Environment Setup(2/2)
� Options � Layout Editor
當遊標靠近 object 時即被吸到 object 邊緣
(建議取消)
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Systems (ARES) Lab.14
Create Ruler
� Window � Create Ruler
� Hot Key:k
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Systems (ARES) Lab.15
Rectangle
� Create � Rectangle
� Hot Key:r
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Systems (ARES) Lab.16
Clear All Rulers
� Window � Clear All Rulers
� Hot Key:shift+k
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Systems (ARES) Lab.17
Polygon
� Create � Polygon
� Hot Key:shift+p
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Systems (ARES) Lab.18
Stretch
� Edit � Stretch
� Hot Key:s
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Systems (ARES) Lab.19
Move
� Edit � Move
� Hot Key:m
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Systems (ARES) Lab.20
Copy
� Edit � Copy
� Hot Key:c
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Systems (ARES) Lab.21
Path
� Create � Path
� Hot Key:p
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Systems (ARES) Lab.22
Merge
� Edit � Merge
� Hot Key:shift+m
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Systems (ARES) Lab.23
Chop
� Edit � Other � Chop
� Hot Key:shift+c
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Systems (ARES) Lab.24
Instance Cell (1/2)
� Create � Instance
� Hot Key:i
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Systems (ARES) Lab.25
Instance Cell (2/2)
� Hot Key:� Shift+f:顯示Instance內容
� Ctrl+f :隱藏Instance內容
Shift+f
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Systems (ARES) Lab.26
Shift+f
Ctrl+f
Flatten
� Edit � Hierarchy � Flatten
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Systems (ARES) Lab.27
Contact
� Create � Contact
� Hot Key:o
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Systems (ARES) Lab.28
Label
� Create � Label
� Hot Key:l
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Systems (ARES) Lab.29
Split
� Edit � Other � Split
� Hot Key: Ctrl+s
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Systems (ARES) Lab.30
Layout’s Hot Key
F2 save p create path
m move c copy
s stretch del delete
u undo i create instance
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Systems (ARES) Lab.31
o create contact ^s split
^z/Z zoom in/zoom out r rectangle
k/K ruler/clear all ruler l label
q properties f fit all
Stream Out
� CIW:File � Export � Stream…
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Systems (ARES) Lab.32
Stream In
� CIW:File � Import � Stream…
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Systems (ARES) Lab.33
Inverter Layout Diagram
P MOS
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Systems (ARES) Lab.34
N MOS
Cross Section vs. Layout View
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Systems (ARES) Lab.35
Design Rules Check (DRC)(1/7)
� Calibre � Run DRC
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Systems (ARES) Lab.36
Design Rules Check (2/7)
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Systems (ARES) Lab.37
Design Rules Check (3/7)
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Systems (ARES) Lab.38
Design Rules Check (4/7)
� Setup � DRC Options
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Systems (ARES) Lab.39
� Run DRC
Design Rules Check (5/7)
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Systems (ARES) Lab.40
Design Rules Check (6/7)
� View �� Show Empty Checks
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Systems (ARES) Lab.41
Design Rules Check (7/7)
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Systems (ARES) Lab.42
儲存儲存儲存儲存Runset File
� Calibre的一些設定,如Rule File的位置、產生檔案放置的位置,都可以儲存在Runset File。
� Calibre DRC視窗:
新的runset file
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Systems (ARES) Lab.43
新的runset file讀取runset file
儲存
另存
Previous Work for LVS(1/2)
1. Type I
Type II
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Systems (ARES) Lab.44
Type I can’t find “top cell name”!!
2.
Previous Work for LVS(2/2)
Modify “pch” & “nch” to “p” & “n”
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Systems (ARES) Lab.45
Schematic
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Systems (ARES) Lab.46
Layout vs. Schematic (LVS)(1/9)
SchematicLayout
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Systems (ARES) Lab.47
Layout vs. Schematic (2/9)
� Calibre � Run LVS
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Systems (ARES) Lab.48
Layout vs. Schematic (3/9)
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Systems (ARES) Lab.49
檔名最好不要跟自己寫的Spice檔 (**.sp)相同,檔案容易被覆蓋
Layout vs. Schematic (4/9)
想從Schematic直接驗證 :� On用自己的Spice檔驗證 :� Off
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Systems (ARES) Lab.50
一個Spice檔裡,可能有許多Cell(Subckt),選擇你所要驗證的Cell
Layout vs. Schematic (5/9)
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Systems (ARES) Lab.51
Layout vs. Schematic (6/9)
� Setup � LVS Options
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Systems (ARES) Lab.52
Layout vs. Schematic (7/9)
� Run LVS
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Systems (ARES) Lab.53
Layout vs. Schematic (8/9)
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Systems (ARES) Lab.54
Layout vs. Schematic (9/9)
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Systems (ARES) Lab.55
PEX (1/9)
� Calibre � Run PEX
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Systems (ARES) Lab.56
PEX (2/9)
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Systems (ARES) Lab.57
PEX (3/9)
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Systems (ARES) Lab.58
此處的設定與 LVS 相同
PEX (4/9)
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Systems (ARES) Lab.59
PEX (5/9)
� Setup � PEX Options
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Systems (ARES) Lab.60
PEX (6/9)
� Run PEX
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Systems (ARES) Lab.61
PEX (7/9)
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Systems (ARES) Lab.62
� Go to Line: 2601
PEX (8/9)3.存檔離開,重新Run PEX
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Systems (ARES) Lab.63
1.開始編輯模式
2. rules檔的路徑修改到自己資料夾的絕對路徑
PEX (9/9)
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Systems (ARES) Lab.64
Post-Layout Simulation
� Modify *.pex.netlist file� Run Hspice simultion� Watch the waveform
with Debussy
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Systems (ARES) Lab.65
Buffer Example
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Systems (ARES) Lab.66
DRC
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Systems (ARES) Lab.67