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Challenges & Opportunities for 3DIC TSV BasedProductsChallenges & Opportunities for 3DIC TSV BasedProducts
Ron HuemoellerSVP, Adv. 3D Platform Develop
October 27, 2011
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Stacked CSPStacked CSP Migration toMigration to TSVTSV
2011 Amkor Technology, Inc. 2 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
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FCBGAFCBGA Migration toMigration to TSVTSV
2011 Amkor Technology, Inc. 3 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
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TSV Industry Product DevelopmentTSV Industry Product Development
Vertical Stacking
Many top tier customers engaged with several years of development completed
Today CSP focused on 28nm CMOS scaling to 20/22nm
Both wafer finishing and pre-finished wafer process flows being used
Interposer Side by Side Stacking
2011 Amkor Technology, Inc. 4 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
any op er cus omers engage w severa years o eve opmen comp e e
All large package body focused
Both wafer finishing and pre-finished wafer process flows being used
Logic on Interposer
Multiple logic die on single thinned interposer
Logic + Memory on Interposer
Single logic die + multiple memory stacks on single thinned interposer
Other passive components in some cases
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Interposer Required
Interposer Required
Si InterpT + DDRT + Logic
Apps ProcessorT + DDR
GPU, CPU
Smart Phone / Tablet
MEMsT
Mobile Devices
TSV Production InterceptsTSV Production Intercepts Amkor ViewAmkor View
2011 Amkor Technology, Inc. 5 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
All Products planning on 22/20nm in future platforms for TSV
2012 2013 2014 20152011
ProductionSince 2010
Interp. Reqd
Memory (DDRT)
Si InterposerT + Logic
Logic Backside Metal
ASIC, FPGA
Power Amp.
Server, Wide I/O
Die with SV indicated by = T
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Logic 1
Logic 1
Logic 1
Logic 2
Cache
Logic 2
AnalogLogic
1
Logic2
Cache
Analog
Multi-DieInter oser
Traditional
SOC
Lo ic
Logic Logic
MonolithicSOC
New !!
3DIC TSV Product Opportunities3DIC TSV Product Opportunities
2011 Amkor Technology, Inc. 6 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
Focus process node development on specific application functionalities
Reduces complexity and mask layer count of process node
Reduces advanced process node Time to Market
Improves wafer yield
Reduces wafer start cost
Improves performance, power, and area of each application functionality
SOCLogic Logic
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Primary Drivers for InterposersPrimary Drivers for Interposers
M
emoryBus
Speed
LowerPower
FabYield
Ne
wMarkets
Stress
Re
ductionin
TopDie
Wide
Parallel
Busses
Wide
Parallel
Busses
Departition
Si InterpT + DDRT + Logic
2011 Amkor Technology, Inc. 7 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
Gate to
Gate
Routing
between
Die
Deconstruc
t
Smaller Die
Departition
(e-DRAM)
Integrate
Hetero-
geneous
Die
Si InterpT + Logic
Si InterpT + Logic + SERDES
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Wafer Finish
Can be at eitherFoundry or OSAT
Silicon Interposer Logistic ChallengeSilicon Interposer Logistic Challenge
2011 Amkor Technology, Inc. 8 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
Business Concerns : Ownership of TSV related failures Cost
Agreed to metric for known good Wafer
Technical Concerns : BOM Compatibility
Same bump metallurgies
Same passivation materials Thin wafer handling / shipping
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Silico
Micro CopperMicro Copper
Pillar BumpingPillar Bumping
MicroMicro JoiningJoining
ThermalThermal
TSV Product ChallengesTSV Product Challenges
Technology IntegrationTechnology Integration
2011 Amkor Technology, Inc. 9 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
SubstrateInterposer
n
UnderfillUnderfill
SubassemblySubassembly
&&
PackagePackage
WarpageWarpage
TSV RevealTSV Reveal
Thin WaferThin WaferHandlingHandling
Interposer ThinningInterposer Thinning
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TSV Reveal, Isolation and Passivation
Key : No damage to silicon, liner or tip
Critical : No copper residue on surface
Wafer Finishing of TSV DevicesWafer Finishing of TSV Devices
2011 Amkor Technology, Inc. 10 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPSAmkor Business Proprietary
Silicon Etch Recess
Ni Au on Copper Via
Grind Expose TSV
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Wafer Finishing of TSV Devices, cont.Wafer Finishing of TSV Devices, cont.
2011 Amkor Technology, Inc. 11 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
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De-bonding both 200mm and 300mm wafers with largeC4 bumps on back side of wafer very challenging
Wafer breakage, bump deformation, foreign material allpresent challenges
200/300mm Thin Wafer Handling De-bonding
Top Wafer Finishing ChallengeTop Wafer Finishing ChallengeThin Wafer HandlingThin Wafer Handling
2011 Amkor Technology, Inc. 12 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
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Die-Die / Die-Substrate Joining
Micro bump uniformity ; Method of Join ; Materials
Die-Die X-Y Spacing Fillet sizes and pad metallurgy
Process assy sequence ; Micro-join method & Matls
Thermal & Power Management
Assembly
Process Flexibilityis
REQUIRED
Top TSV Assembly ChallengesTop TSV Assembly Challenges
2011 Amkor Technology, Inc. 13 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
Use of Lids, Stiffeners & Passives
Underfill/Resin bleed, adhesive compatibility
Process assy sequence ; Micro-join method & Matls
Warpage Control
Interposer warpage ; Substrate warpage
Top die warpage top die area density/distribution
Intermediate e-Test Points
Process assembly sequence
Die to DieDie to SubstrateDie to Wafer
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Vertical Stacking Side-Side Stacking
Many Assembly Flows in Use TodayMany Assembly Flows in Use Today
2011 Amkor Technology, Inc. 14 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
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Thermo-Compression Bond + Non Conductive Paste (NCP)
Thin die handling capability to 50m
Material dispense critical
TSV CSP Vertical AssemblyTSV CSP Vertical Assembly
2011 Amkor Technology, Inc. 15 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
Pitch 40m today ; 30m 2011Pitch 40m today ; 30m 2011Pillar to NiPillar to Ni--Au Pad as standardAu Pad as standard
Chip
Chip
Cu Pillar withCu Pillar with SnAgSnAg BumpsBumps4040m todaytoday
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Assembly Experience on Interposer
Substrates range from 35mm up to 55mm
Interposer thickness as thin as 60um, buttypically at100um
DRAM
DRAM
GPU
TSV Silicon Interposer AssemblyTSV Silicon Interposer Assembly
2011 Amkor Technology, Inc. 16 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
Pitch 40m today ; 30m 2012Pitch 40m today ; 30m 2012 80m Tall Plated SnAg Bumps80m Tall Plated SnAg Bumps
Pitch
150m today ;
130m 2012Pitch
150m today ;
130m 2012
Chip
Chip
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Initial Underfill MRT, L4
TSV Silicon Interposer ReliabilityTSV Silicon Interposer Reliability
2011 Amkor Technology, Inc. 17 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
48 ours HAST 264 Hours
Passed MRT + HAST: 110C, 85% RH, 264 Hours
Courtesy of Xilinx, TSMC, Amkor
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ASIC (die to die = face to face)
Multiple Die on Interposer ; 100m thick, 10m TSV at 210m pitch
Logic at 40m pitch bump with 25m dia. ; over 200k micro-bumps
Passed Level 4 MRT ; TC Condition B 1000 cycles ; HTS 1000 hrs
Handset 45nm Baseband (die to die = face to back)
~
TSV Reliability DataTSV Reliability Data GeneralGeneral
2011 Amkor Technology, Inc. 18 R.Huemoeller Oct-11Amkor Info. for Controlled Release at AZ IMAPS
Logic ~ 50m thick with 10m TSV at 40um pitch ; either peripheral orarea array bump pitch to substrate
Passed MRT L3 260C (3x reflow) ; T/C-B 1000 cycles ; HTS 1000 hrs
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Thank You!