5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
As used on Trenz carrier.
Cheaper alternative - different pin-out.
<Doc> 1
EMC2-DP - Ethernet
C
1 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
PHY_MDI0_PPHY_MDI0_N
PHY_MDI1_PPHY_MDI1_N
SEIC_PHY_LED2
SEIC_PHY_LED1
PHY_MDI2_PPHY_MDI2_N
PHY_MDI3_NPHY_MDI3_P
V33OUT
R110 0R
C75100nF
75 75
1
2
3
6
75 75
7
4
5
8
J8Wurth 7499111121A
1
23
6
10
4
57
8
1112
1314
9
15
16
T0+
T0-T1+
T1-
SH
T2+
T2-T3+
T3-
LED1-ALED1-K
LED2-ALED2-K
VCC
Case
Case
R34 240R
R112 0R
75 75
1
2
3
6
75 75
7
4
5
8
J8ABel SI-61001-F
2
34
5
10
6
78
9
1112
1314
1
15
16
T0+
T0-T1+
T1-
SH
T2+
T2-T3+
T3-
LED1-ALED1-K
LED2-ALED2-K
VCC
Case
Case
R113 0R
Q3DDTC143XE
3
1
2 C74 100pF
R35 1M
Q4DDTC143XE
3
1
2
R111 0R
R33 240R
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NC on 701
NC on 701
Insert jumper when no Trenz
module is present to enable
on-board 3.3V supply.
<Doc> 1
EMC2-DP - FMC
C
2 13Tuesday, September 15, 2015
Title
Size Document Number Rev
Date: Sheet of
LA25_P
LA16_P
LA02_N
LA20_N
LA24_P
LA28_P
LA01_CC_P
LA14_P
LA15_N
LA12_N
LA25_N
LA22_N
LA02_P
LA24_N
LA19_P
CK0_M2C_N
LA10_PLA10_N
LA15_P
LA29_N
LA12_P
LA13_N
LA22_P
LA19_N
LA06_N
CK0_M2C_P
fTDI
LA11_N
SLB0_Signal0
SCL
LA08_N
LA29_P
LA00_CC_P
LA23_P
LA13_P
LA21_N
fTCK
LA06_P
LA11_P
LA30_P
LA08_P
LA17_CC_N
LA09_N
LA23_N
LA33_N
fTMS
LA07_N
LA03_N
LA30_N
LA17_CC_P
LA26_N
LA09_P
CK0_C2M_N
fTDO
LA33_P
LA07_P
SDA
LA32_N
LA18_CC_P
LA05_N
LA26_P
LA31_N
CK0_C2M_P
LA04_N
LA21_P
LA32_P
LA18_CC_N
LA05_P
LA16_N
fTRSTLA31_P
LA20_P
LA04_P
LA27_N
LA28_N
LA01_CC_N
LA14_N
LA03_P
LA00_CC_N
fTRSTfTMSfTDO
fTDIfTCK
LA27_P
tFMC_CLK1_PtFMC_CLK1_N
tFMC_CLK0_PtFMC_CLK0_N
FMC_VREF
tFMC_TRZ_CK_NtFMC_TRZ_CK_P
tFMC_TRZ_RX_NtFMC_TRZ_RX_P
tFMC_TRZ_TX_NtFMC_TRZ_TX_P
tFMC_LA18_PtFMC_LA18_N
tFMC_LA10_NtFMC_LA10_P
tFMC_LA06_PtFMC_LA06_N
tFMC_LA26_NtFMC_LA26_P
tFMC_LA23_NtFMC_LA23_P
tFMC_LA17_PtFMC_LA17_N
tFMC_LA13_NtFMC_LA13_P
tFMC_LA09_NtFMC_LA09_P
tFMC_LA05_NtFMC_LA05_P
tFMC_LA01_NtFMC_LA01_P
tFMC_LA25_PtFMC_LA25_N
tFMC_LA20_NtFMC_LA20_P
tFMC_LA12_PtFMC_LA12_N
tFMC_LA08_NtFMC_LA08_P
tFMC_LA03_NtFMC_LA03_P
tFMC_LA00_PtFMC_LA00_N
tFMC_LA32_PtFMC_LA32_N
tFMC_LA19_PtFMC_LA19_N
tFMC_LA15_NtFMC_LA15_P
tFMC_LA11_NtFMC_LA11_P
tFMC_LA07_PtFMC_LA07_N
tFMC_LA04_PtFMC_LA04_N
tFMC_LA02_NtFMC_LA02_P
FMC_SDAFMC_SCL
PRSNT_M2C_L
tFMC_LA16_P
tFMC_LA31_NtFMC_LA31_P
tFMC_LA16_NtFMC_LA14_PtFMC_LA14_N
tFMC_LA22_PtFMC_LA22_N
tFMC_LA21_NtFMC_LA21_P
tFMC_LA29_PtFMC_LA29_N
tFMC_LA28_NtFMC_LA28_P
tFMC_LA30_NtFMC_LA30_P
tFMC_LA33_PtFMC_LA33_N
tFMC_LA24_PtFMC_LA24_N
tFMC_LA27_PtFMC_LA27_N
V12P
V12P
V12P V12P
V33OUT
V33FMC
V33FMCV33IN
V33IN
V33FMC
VCCIO35
VCCIO35VCCIO35
VCCIO35
V33FMC
V33FMC
V33FMC V33FMC V33FMCV33FMC
VCCIO35
V33OUT
VCCIO35 VCCIO35
C622uF
C322uF
C210uF
FMC1A
FMC-LPC
C1C2C3C4C5C6C7C8C9
C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32C33C34C35C36C37C38C39C40
GNDDP0_C2M_PDP0_C2M_NGNDGNDDP0_M2C_PDP0_M2C_NGNDGNDLA06_PLA06_NGNDGNDLA10_PLA10_NGNDGNDLA14_PLA14_NGNDGNDLA18_P_CCLA18_N_CCGNDGNDLA27_PLA27_NGNDGNDSCLSDAGNDGNDGA012P0VGND12P0VGND3P3VGND
R310k0
R110k0
R5510k0
R5610k0
C8100nF
C722uF
R410k0
C522uF
U8TPS27082LDDCR
1
23
4
5
6GND
VOUTVOUT
VIN
ON/OFF
R1/C1
JP9HEADER 4X2
1 23 45 67 8
C7610nF 16V
R210k0
C110uF
FMC1D
FMC-LPC
H1H2H3H4H5H6H7H8H9
H10H11H12H13H14H15H16H17H18H19H20H21H22H23H24H25H26H27H28H29H30H31H32H33H34H35H36H37H38H39H40
VREF_A_M2CPRSNT_M2CGNDCK0_M2C_PCK0_M2C_NGNDLA02_PLA02_NGNDLA04_PLA04_NGNDLA07_PLA07_NGNDLA11_PLA11_NGNDLA15_PLA15_NGNDLA19_PLA19_NGNDLA21_PLA21_NGNDLA24_PLA24_NGNDLA28_PLA28_NGNDLA30_PLA30_NGNDLA32_PLA32_NGNDVADJ
C9100nF
R3610k
C422uF
C100R
FMC1C
FMC-LPC
G1G2G3G4G5G6G7G8G9
G10G11G12G13G14G15G16G17G18G19G20G21G22G23G24G25G26G27G28G29G30G31G32G33G34G35G36G37G38G39G40
GNDCK0_C2M_PCK0_C2M_NGNDGNDLA00_P_CCLA00_N_CCGNDLA03_PLA03_NGNDLA08_PLA08_NGNDLA12_PLA12_NGNDLA16_PLA16_NGNDLA20_PLA20_NGNDLA22_PLA22_NGNDLA25_PLA25_NGNDLA29_PLA29_NGNDLA31_PLA31_NGNDLA33_PLA33_NGNDVADJGND
R37200k
C110R
FMC1B
FMC-LPC
D1D2D3D4D5D6D7D8D9
D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31D32D33D34D35D36D37D38D39D40
PG_C2MGNDGNDGK0_M2C_PGK0_M2C_NGNDGNDLA01_P_CCLA01_N_CCGNDLA05_PLA05_NGNDLA09_PLA09_NGNDLA13_PLA13_NGNDLA17_P_CCLA17_N_CCGNDLA23_PLA23_NGNDLA26_PLA26_NGNDTCKTDITDO3P3VAUXTMSTRSTGA13P3VGND3P3VGND3P3V
JP6HEADER 2
1 2
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
<Doc> 1
EMC2-DP - HDMI
C
3 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
HDMI_TXC_PHDMI_TXC_N
HDMI_TX0_PHDMI_TX0_N
HDMI_TX1_PHDMI_TX1_N
HDMI_TX2_PHDMI_TX2_N
HDMI_SDA
HDMI_INT
HDMI_SCL
HDMI_VSYNC
HDMI_HSYNC
HDMI_CLK
HDMI_DE
HDMI_D0HDMI_D1HDMI_D2HDMI_D3HDMI_D4HDMI_D5HDMI_D6HDMI_D7HDMI_D8HDMI_D9HDMI_D10HDMI_D11
HDMI_INTHDMI_SDAHDMI_SCL
CT_HPD
LS_OE
CEC_CLK
SPDIF_OUTSPDIF_IN
V5
DVDD_HDMI
DVDD_HDMI
AVDD_HDMI
PLVDD_HDMI
MVDD_HDMI
V18 DVDD_HDMI
V18 AVDD_HDMI
PLVDD_HDMIV18
MVDD_HDMIV33OUT
V33OUT
VCCIO34
C37100nF
C14100nF
C3810nF
C2810uF
C12 1uF
C84100nF
R749R9
R10887R
C20100nF
L2BLM21PG221SN1D
U2TPD12S016PWR
123456789
101112
242322212019181716151413
CEC_ASCL_ASDA_AHPD_ALS_OEGNDCEC_BSCL_BSDA_BHPD_BVCC5VCT_HPD
VCCAD2+D2-D1+D1-
GNDD0+D0-
CLK+CLK-GND
5V_OUT
R5 DNF
U1AADV7511KSTZ
2
98
79
97
969594939291908988878685848382818078747372717069686766656463626160595857
3332
3635
4039
4342
30
48
50
5354
5251
5556
45
VSYNC
HSYNC
CLK
DE
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31D32D33D34D35
TXC+TXC-
TX0+TX0-
TX1+TX1-
TX2+TX2-
HPD
CEC
CEC_CLK
DDCSCLDDCSDA
HEAC+HEAC-
SCLSDA
INT
C36100nF
C151uF
C13 1uF
C3410nF
L4BLM21PG221SN1D
C2710nF
C21100nF
U1BADV7511KSTZ
10
11
16
17
9
38
12131415
345678
46SPDIF
MCLK
SCLK
LRCLK
DSD_CLK
PD
I2S0I2S1I2S2I2S3
DSD0DSD1DSD2DSD3DSD4DSD5
SPDIFOUT
L3BLM21PG221SN1D
HDMI1HDMI-RA-19-TYPEA
21
3
54
6
87
9
1110
12
1413
1516
1819
20212223
17
D2 SHIELDD2+
D2-
D1 SHIELDD1+
D1-
D0 SHIELDD0+
D0-
CK SHIELDCK+
CK-
NC.14CE REMOTE
DDC CLKDDC DATA
+5VHP DET
MTG1MTG2MTG3MTG4
GND
C2610nF
C23100nF
C4010uF
R649R9
C2510nF
C8710nF
C1910uF
R8 DNF
C22100nF
L1BLM21PG221SN1D
C29100nF
C17100nF
C85100nF
R9 4k7
C4210nF
C3510uF
C18100nF
C2410nF
C3910nF
U1CADV7511KSTZ
119497677
2425
21
26
293441
47
18202223273137447599100
28DVDDDVDDDVDDDVDDDVDD
PVDDPVDD
PLVDD
BGVDD
AVDDAVDDAVDD
MVDD
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
R_EXT
C16100nF
C86100nF
C41100nF
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
3.3V from PCIe or external
power connector.
3V battery input.
<Doc> 1
EMC2-DP - JTAG/RST/BAT/MAC
C
4 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
TCK
TDI
nRESETIN
TDO
TMS
VBUS_SENSE
VBAT
TMSTCKTDOTDI
POR#
I2C0_SDAI2C0_SCL
RTC_INT#
SEIC_UART_RXSEIC_UART_TX
GNDGND
VCCJTAG
V33OUT
V33IN
V33IN
V33IN
V33IN
V33OUT
BAT1HEADER 2
12
R10310k0
C9747pF
J9USB micro B
12345
6
7
8
9
C182100nF
Y1CRYSTAL32.768kHz
C9847pF
C55100nF
U14FT230XS
1
2
3
4
5
6
7
89
10
11
12
13
1415
16
TXD
RTS#
VC
CIO
RXD
GN
D
CTS#
CBUS2
USBDPUSBDM
3V3OUT
RESET#
VC
C
GN
D
CBUS1CBUS0
CBUS3
SC10F2
R10410k0
D1BAV70
1
2
3
JP2HEADER 2
1 2
R53 1M0
U2924AA02E64T
1
23
4
5
SCL
VssSDA
Vcc
NC
R51 4k7
R50 27R
C99 4n7F
U3
TLC7733
723
651
4 8
SENSERESINCT
RESETRESET
REFGND VCC
U28DS1337+
1 2
3
4
56 7
8
X1
X2
INTA
GN
D
SDASCL SQW/INTB
VC
C
SW1SW PUSHBUTTON
R5210k0
JP1
HEADER 7X2
1 23 45 67 89 1011 1213 14
R54100R
C96100nF
R49 27R
R114K7
C431uF Ceramic 0603
R38DUALR 0R
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LVTTL & diff
MIO is at 3.3V
1v8
<Doc> 1
EMC2-DP - Misc.
C
5 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
TTL1
TTLN
TTL2
TTL3
SDD0
SDD1
SDD2
SDD3
SDCMD
SDCLK
TTL0
TTLP
WIRE1
TTLPTTLN
TTL0
TTL1
TTL2
TTL3
SD_SW
SD_CMD
SD_D0
SD_CLK
SD_D1
SD_D3
SD_D2
I2C0_SCL
I2C0_SDA
PPS1
LED3
LED4
WIRE1
LED2
LED1
LEDT1LEDT2
V5
V33OUT
V33OUT
VIOB V33OUT
V33OUT
VCCIO34
VCCIO34
V33OUT
VCCIO35
V33OUTVCCIO34
VCCIO34
V33OUT
V33OUT
V33OUT
V33OUT
U5DS2432
123 4
56
GND1-WIRENC NC
NCNC
R15 390R
C77100nF
U4
microSD
12345678
910
1112131415
DATA2DATA3/CD(CS)CMD(DI)VDDCLK(SCLK)VSSDATA0(DO)DATA1
SW-1SW-2
TABTABTABTABTAB
U16IP4220CZ6
1
2
3 4
5
6IO1
GND
IO2 IO3
Vp
IO4
Q1DDTC143XE
3
1
2
U13MPU-9250
123456
7 8 9 10
11
12
131415161718
19
20
21
22
23
24
RESVNCNCNCNCNC
AU
X_C
LV
DD
IOA
D0/S
DO
RE
GO
UT
FS
YN
CIN
T
VDDNCNCNCNC
GND
RE
SV
RE
SV
AU
X_D
AC
SS
CL/S
CK
SD
A/S
DI
C9410nF
U9TXS02612RTWR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1516
17
18
19
20
21
22
23
24
DAT2A
GND
DAT3A
CMDA
VCCA
DAT0A
DAT1A
DAT2B1
CLKA
DAT3B1
GND
CMDB1
CLKB1
DAT0B1
DAT1B1DAT1B0
VCCB1
DAT0B0
CLKB0
CMDB0
VCCB0
DAT3B0
DAT2B0
SEL
R13 390R
C100100nF
R18100R
R171k0
D3 LED
1 2
C44100nF
R16 390R
R19100R
Q2DDTC143XE
3
1
2
JP3
HEADER 4X2
1 23 45 67 8
C78100nF
C1011uF
C102100nF
R14 390R
D5 LED
1 2
R462k26
C93100nF
FAN1HEADER 2
12
U18MAX3394EETA+
12
34
5
67
8
9
VCCEN
I/OVcc1I/OVcc2
GND
I/OVl2I/OVl1
Vl
PAD
D4 LED
1 2
L12BLM21PG221SN1D
R472k26
U15IP4220CZ6
1
2
3 4
5
6IO1
GND
IO2 IO3
Vp
IO4C95100nF
R124k7
D2 LED
1 2
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SATA_PWR N/C
SATA_DET0
PI2DBS212CBTU04083
1/16 W, V=5V, Rmin=400.
If HOST is low then drive
CPU_DIR=GND. Stack-up is only
option in HOST mode. When not
in HOST mode, then float
CPU_DIR.
<Doc> 1
EMC2-DP - PCIe
C
6 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
DIR
SMBALERT
PWRGOOD
PSON#
PCLKP3
SMBDATSMBCLK
PCLKP2
VL33
PCLKP1
PCLKN3
PCIeRST
CPU_DIR
VL33
PCLKN1
PCLKN2
V5SB V5SB
USB_1P USB_1NUSB_0P USB_0N
PCLKBP
PSON#
V5SB
VL33
PCLKN2
SMBALERT
SMBDAT
PCLKTP
USB_1PUSB_0N
VL33
PCLKP3
V5SB
USB_1N
PCLKTNPCLKN3
SMBCLK
PCLKN1
PCIeRST
PCLKP2
USB_0P
PWRGOODCPU_DIR
PCLKP1
SATA_PCI_RX_PSATA_PCI_RX_N
SATA_PCI_TX_NSATA_PCI_TX_P
SATA_PCI_TX_NSATA_PCI_TX_P
SATA_PCI_RX_PSATA_PCI_RX_N
PCLKBN
CPU_DIR
PCIeBotTXn0
PCIeTopTXn2
PCIeBotRXn0PCIeTopRXp0PCIeTopRXn0
PCIeBotRXn3
PCIeTopTXp2 PCIeBotTXp3
PCIeTopRXn2
PCIeBotTXn2
PCIeTopTXp1
PCIeBotRXn2
PCIeBotRXn1
PCIeBotTXp2
PCIeTopTXn1PCIeTopTXp0
PCIeBotRXp2
PCIeBotRXp0PCIeBotRXp1
PCIeBotTXn3
PCIeTopRXp2
PCIeTopTXn3
PCIeTopRXn1PCIeTopRXp1
PCIeBotTXp0
PCIeTopTXp3
PCIeBotTXn1PCIeTopTXn0PCIeBotTXp1
PCIeBotRXp3PCIeTopRXp3PCIeTopRXn3
PE0CLKPPE0CLKN
PE1CLKPPE1CLKN
PE2CLKPPE2CLKN
PE3CLKPPE3CLKN
PCIeRST#
I2C1_SCLI2C1_SDA
DIR
tSATA_SEC_TX_PtSATA_SEC_TX_N
SATA_TRZ_RX_NSATA_TRZ_RX_P
tSATA_SEC_RX_NtSATA_SEC_RX_P
SATA_TRZ_TX_PSATA_TRZ_TX_N
PCIeCLKPPCIeCLKN
HOST#
V5V12P
V5
V5 V5 V5
V18
V5
V33
V18F
V18F
V33
R411k0
JAB1
PCIe104ConnectorA
1 2
3 4
5 6
7 8
9 10
11 12 13 14
15 16
17 18 19 20
21 22
23 24 25 26
27 28
29 30 31 32
33 34
35 36 37 38
39 40
41 42 43 44
45 46 47 48 49 50 51 52 53 54
55 56
57 58 59 60
61 62
63 64 65 66
67 68
69 70 71 72
73 74
75 76 77 78
79 80
81 82 83 84
85 86
87 88 89 90
91 92
93 94 95 96
97 98
99 100101 102
103 104
105 106
107 108
109 110111 112
113 114
115 116117 118
119 120
121 122123 124
125 126
127 128129 130
131 132
133 134135 136
137 138
139 140141 142
143 144
145 146147 148
149 150
151 152153 154
155 156
157158159
Reserved (GPIO0) PE_RST#
3.3V 3.3V
Reserved (HS1+) Reserved (HS0+)
Reserved (HS1-)Reserved (HS0-)
GND GND
PEx1_1Tp PEx1_0TpPEx1_1Tn PEx1_0Tn
GND GND
PEx1_2Tp PEx1_3TpPEx1_2Tn PEx1_3Tn
GND GND
PEx1_1Rp PEx1_0RpPEx1_1Rn PEx1_0Rn
GND GND
PEx1_2Rp PEx1_3RpPEx1_2Rn PEx1_3Rn
GND GND
PEx1_1Clkp PEx1_0ClkpPEx1_1Clkn PEx1_0Clkn
5V_Always 5V_Always
PEx1_2Clkp PEx1_3ClkpPEx1_2Clkn PEx1_3Clkn
CPU_DIR PWRGOODSMB_DAT PEx16_x8_x4_ClkpSMB_CLK PEx16_x8_x4_ClknSMB_ALERT PSON#Reserved / WAKE# PEG_ENA#
GND GND
PEx16_0T(8)p PEx16_0T(0)pPEx16_0T(8)n PEx16_0T(0)n
GND GND
PEx16_0T(9)p PEx16_0T(1)pPEx16_0T(9)n PEx16_0T(1)n
GND GND
PEx16_0T(10)p PEx16_0T(2)pPEx16_0T(10)n PEx16_0T(2)n
GND GND
PEx16_0T(11)p PEx16_0T(3)pPEx16_0T(11)n PEx16_0T(3)n
GND GND
PEx16_0T(12)p PEx16_0T(4)pPEx16_0T(12)n PEx16_0T(4)n
GND GND
PEx16_0T(13)p PEx16_0T(5)pPEx16_0T(13)n PEx16_0T(5)n
GND GND
PEx16_0T(14)p PEx16_0T(6)pPEx16_0T(14)n PEx16_0T(6)n
GND GND
PEx16_0T(15)p PEx16_0T(7)pPEx16_0T(15)n PEx16_0T(7)n
GND GND
SDVO_DAT (PENA#) SDVO_CLK
GND GND
PEx16_0R(8)p PEx16_0R(0)pPEx16_0R(8)n PEx16_0R(0)n
GND GND
PEx16_0R(9)p PEx16_0R(1)pPEx16_0R(9)n PEx16_0R(1)n
GND GND
PEx16_0R(10)p PEx16_0R(2)pPEx16_0R(10)n PEx16_0R(2)n
GND GND
PEx16_0R(11)p PEx16_0R(3)pPEx16_0R(11)n PEx16_0R(3)n
GND GND
PEx16_0R(12)p PEx16_0R(4)pPEx16_0R(12)n PEx16_0R(4)n
GND GND
PEx16_0R(13)p PEx16_0R(5)pPEx16_0R(13)n PEx16_0R(5)n
GND GND
PEx16_0R(14)p PEx16_0R(6)pPEx16_0R(14)n PEx16_0R(6)n
GND GND
PEx16_0R(15)p PEx16_0R(7)pPEx16_0R(15)n PEx16_0R(7)n
GND GND
5V5V12V
0
0
1
0
1
0
0
1
0
0
1
0
U12TS2PCIE2212
A1
A4B4
A2B3
B1C2
D1D2
F1F2
H1G2
J2H3
J4H4
J9
A6B6
A8B7
B9C8
D9D8
F9F8
H9G8
J8H7
J6H6
A5
B2
B8
E1
E9
H2
H8
J5
B5
E2
E8
H5
CTRL0
TxSA0pTxSA0n
TxSB0pTxSB0n
RxSA0pRxSA0n
RxSB0pRxSB0n
TxSA1pTxSA1n
TxSB1pTxSB1n
RxSA1pRxSA1n
RxSB1pRxSB1n
CTRL1
TxDA0pTxDA0n
TxDB0pTxDB0n
RxDA0pRxDA0n
RxDB0pRxDB0n
TxDA1pTxDA1n
TxDB1pTxDB1n
RxDA1pRxDA1n
RxDB1pRxDB1n
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
Vdd
Vdd
Vdd
Vdd
C4733uF TantA
o/c
U30SN74AHC1G09
1
2
3
4
5
A
B GN
D YVC
C
R114470R
C89100nF
JP10HEADER 2
12
C4533uF TantA
R20 22k0
FLTR1FLTR1
1 3
2
IN OUT
GN
D
C88100nF
C91100nF
R2112k0
C4633uF TantA
J2PCIe104Connector1bank
1 2
3 4
5 68
9 10
11 12 13 14
15 16
17 18 19 20
21 22
23 24 25 26
27 28
29 30 31 32
33 34
35 36 37 38
39 40
41 42 43 44
45 46 47 4849 5051 52
7
53
USB_OC# PE_RST#
3.3V 3.3V
USB_1P USB_0PUSB_0N
GND GND
PEx1_1Tp PEx1_0TpPEx1_1Tn PEx1_0Tn
GND GND
PEx1_2Tp PEx1_3TpPEx1_2Tn PEx1_3Tn
GND GND
PEx1_1Rp PEx1_0RpPEx1_1Rn PEx1_0Rn
GND GND
PEx1_2Rp PEx1_3RpPEx1_2Rn PEx1_3Rn
GND GND
PEx1_1Clkp PEx1_0ClkpPEx1_1Clkn PEx1_0Clkn
5V_Always 5V_Always
PEx1_2Clkp PEx1_3ClkpPEx1_2Clkn PEx1_3Clkn
CPU_DIR PWRGOODSMB_DAT RSVD0SMB_CLK RSVD1SMB_ALERT PSON#
USB_1N
V5
C90100nF
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NC
NC
100MHz
NC
NC
NC
Host select jumper. Insert
to set mode to HOST.
Clock
tri-state.
Select local 100MHz clock when
in HOST mode and drive to PCIe
top connector, PCIe packet
switch, and Trenz module.
When in 'add-on' mode select
top or bottom 1-lane clock.
Only drive to packet switch
and Trenz module (tri-state
PCIe clock driver).
From PCIe top/bottom
selector.
To Trenz.
HCSL
HCSL Source
TerminationNC
NC
LVDS
Fir 0R for DC
coupled LVDS.
NC
NC
NC
NC
NC
NC
NC
NC
NC
If PCIe reset input is low or power
on reset is low, then reset the
Trenz module (active low) and the
PCIe switch.
If power on reset is low and the
board is a host, then drive PCIeRST
low (open collector with pull-up).
The PCIeRST signal also goes to an
FPGA I/O pin. The bank voltage can
be 1.8v or 3.3v (jumper), so the AND
gate has an o/c output.
NC
PU
PU
PU
NC
PORTCFG 01 (LH)
x2, x1, x1, x1,
x1
NC
NC
NC
NC
Test
points.
TxBot0 <> TxBot1 is not an
issue as the EMC board will be
stack-bottom when a host.
In HOST/ROOT mode, DIR=GND
Stck-up, DIR=GND.
<Doc> 1
EMC2-DP - PCIe Switch
D
7 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
PERN7PERP7
HOST#
PCIeLocalP
PCIeLocalN
V33CLKBUF
HOST#
PEX_REFCLKNPEX_REFCLKP
V33CLKBUF
PETP4
PETN5
PETP7PETN7
PETN6
PCIeSWRST#
PCIeSWRST#
HOST#
PETN4
PETP5
PETP6
PORTSEL0PORTSEL1PORTSEL2PORTSEL3
HOST#
HOST#
PERP5PERN5
PERP6PERN6
HOST#
PERP4PERN4
PETPC4PETNC4
PETPC5PETNC5
PETPC6PETNC6
PCIeBotXn0
PCIeBotXXn0PCIeBotXXp0
PETPC7
PCIeBotXp0
PETNC7
PCIeCLKN
PCIeCLKP
PE0CLKP
PE3CLKN
PE0CLKN
PE3CLKP
PE1CLKP
PE2CLKNPE2CLKP
PE1CLKN
PCLKP0
PCLKN0
POR#
PCIeRST#TRENZRST#
PCIeRST18#
PE1TXN0
PE1TXP0
PE1TXN3
PE1TXP3
PE1RXP0
PE1RXN0
PE1RXP3
PE1RXN3
HOST#
I2C0_SCLI2C0_SDA
LED3LED4
DIR
PCIeBotRXp3
PCIeBotRXp2
PCIeTopRXp0
PCIeBotRXn1
PCIeTopRXn2
PCIeBotRXp1
PCIeBotRXn2
PCIeTopRXp2
PCIeTopRXn0
PCIeBotRXn3
PCIeTopRXp1PCIeTopRXn1
PCIeBotTXn3
PCIeTopTXp2
PCIeBotTXp2
PCIeTopTXp1
PCIeBotTXn2
PCIeTopTXp0
PCIeBotTXp1
PCIeTopTXn2
PCIeBotTXn1
PCIeTopTXn0
PCIeBotTXp3
PCIeTopTXn1
PCIeBotRXn0PCIeBotRXp0
PCIeBotTXn0PCIeBotTXp0
DIR
PCIeTopTXp3PCIeTopTXn3
PCIeTopRXp3PCIeTopRXn3
VDD25VDD25
VDD25VDD25
VDD25VDD25
VDD25
VDD25VDD25
VDD25
V33
VDD25
VDD25
V25
VDD25
VDD25
V33
V33
V33
V33
V33
V33
V33
V33
V33
V33V33 V33
V33
V33
R7386r6
C105 10nF
C108100nF
R10110k0
C115100nF
R67 42r2
R7086r6
C107220nF
R81390R
R60 42r2
C123 10nF
D8LED
12
C180 100nF
R7286r6
U23SN74AHC1G32
1
2
3
4
5
A
BGN
D4 VC
C
C109220nF
R10210k0
C114100nF
R68 42r2
R854k7
C103220nF
D12LED
12
D7LED
12
R6582R5
R87 100R
R83 100R
R88 1k43
L8BLM21PG221SN1D
R78390R
C113100nF
R86470R
C112 10nF
C104220nF
R77390R
R80390R
X2
OSC_LVPECL_PCIe
1
3
6
4
5
OE
GND
V2.5
CLK
CLK
C106 10nF
C176 100nF
U25SN74AHC1G08
1
2
3
4
5
A
B GN
D YVC
C
L7BLM21PG221SN1D
C175 100nF
C122 10nF
C121 10nF
JP12HEADER 2
12
R89 1k43
R9910k0
R7486r6
C184100nF
R10910k0
R1050R
R844k7
D10LED
12
R6682R5
A-BC-D
A-DC-B
0
1
U20PI3PCIE3442TQFN40
12
34
56
7
89
1011
1213
14
15
16
17
18
1920
2122
2324
2526
27
28
2930
3132
3334
3536
37
38
3940
41
C0+C0-
A1+A1-
C1+C1-
SEL
A2+A2-
C2+C2-
A3+A3-
C3+
GND
C3-
VDD
GND
D3-D3+
B3-B3+
D2-D2+
B2-B2+
GND
VDD
D1-D1+
B1-B1+
D0-D0+
B0-B0+
GND
OE#
A0+A0-
GNDP
C177 100nF
R57127R
R90 100R
o/c
U22SN74AHC1G09
1
2
3
4
5
A
BGN
DY VC
C
C120100nF
R59 42r2
R62 42r2
R7586r6
D9LED
12
JP13HEADER 2
12
R1080R
C119100nF
C183220nF
C179 100nF
C118100nF
R61 42r2
C110220nF
R79390R
A-BC-D
A-DC-B
0
1
US1PI3PCIE3442TQFN40
12
34
56
7
89
1011
1213
14
15
16
17
18
1920
2122
2324
2526
27
28
2930
3132
3334
3536
37
38
3940
41
C0+C0-
A1+A1-
C1+C1-
SEL
A2+A2-
C2+C2-
A3+A3-
C3+
GND
C3-
VDD
GND
D3-D3+
B3-B3+
D2-D2+
B2-B2+
GND
VDD
D1-D1+
B1-B1+
D0-D0+
B0-B0+
GND
OE#
A0+A0-
GNDP
C124220nF
C181 100nF
C117100nF
R64 42r2
R91 1k5
SW2SW DIP-4
1234
8765
R7186r6
D11LED
12
o/c
U26SN74AHC1G09
1
2
3
4
5
A
B GN
D YVC
C
U21APEX8606BA
A3 A4
A5 A6
A9A10
A11A12
B3 B4
B5 B6
B9B10
B11B12
N3
N5
P3
P5
P4N4
P6N6
A1B2
P14
M13
B1
B14
A14
C2
B7A7
A13C12
C13D14D12E12E13
B13
C1
C3
C4
C14
D2D1E3E2E1F2J4J1H1K1M1P2P1L3M2N2K12D3A2
F3
J2
H2G2
J3
F1
K3M3
F14F12
F13E14
G13F11G14
H13
L13
M12
H12
M4
K13
L1
K2L2
J11
G1
J12
J13J14K14H14
F4D13
P13N14M14N13
P7N7B8A8
N8P8
PERP7 PETP7
PERP6 PETP6
PETP5PERP5
PETP4PERP4
PERN7 PETN7
PERN6 PETN6
PETN5PERN5
PETN4PERN4
PERN0
PERN1
PERP0
PERP1
PETP0PETN0
PETP1PETN1
PORTCFG0PORTCFG1
LANE_GOOD0#
LANE_GOOD1#
LANE_GOOD4#
LANE_GOOD5#
LANE_GOOD6#
LANE_GOOD7#
REFCLK_CFCPREFCLK_CFCN
DIODEPDIODEN
JTAG_TRST#JTAG_TMSJTAG_TDIJTAG_TDOJTAG_TCK
FATAL_ERR#
TIMER_EN#
FAST_BRINGUP#
SERDES_MODE_EN#
SHPC_INT#
GPIO0GPIO1GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7GPIO8GPIO9
GPIO10GPIO11GPIO12GPIO13GPIO14GPIO15GPIO16GPIO29GPIO30
PORTSEL0
PORTSEL1
PORTSEL2PORTSEL3
PORTSEL0
PORTSEL1
PORTSEL2PORTSEL3
I2C_SCL0I2C_SDA0
I2C_SCL1I2C_SDA1
I2C_ADDR0I2C_ADDR1I2C_ADDR2
PERST#
NT_RESET#
PLL_BYPASS#
NT_ENABLE#
SSC_SIO_ENABLE#
PROBE_MODE#
SMBUS_EN#
SPARE0#SPARE1#
DEBUG_SEL0
P2P_EN#
INTA#
EE_CS#EE_SKEE_DIEE_DO
RSVD17#RSVD16
TESTMODE0TESTMODE1TESTMODE2TESTMODE3
REXT_A0REXT_B0REXT_A1REXT_B1
REFCLKPREFCLKN
U27Si53302
1
23
910
6
12
23
13
1415
16
18
1920
21
1744
34
3738
3132
33
4041
4243
45
78
3635
3029
2726
2524
22
1128
39
DIVA
SFOUTA1SFOUTA0
Q0Q0
GND
VDD
CLK_SEL
LOS0
CLK0CLK0
OEA
OEB
CLK1CLK1
LOS1
VREFVDDOA
VDDOB
Q5Q5
SFOUTB0SFOUTB1
DIVB
Q4Q4
Q3Q3
Q2Q2
Q1Q1
Q6Q6
Q7Q7
Q8Q8
Q9Q9
GND
NCNC
GND
R10010k0
L9BLM21PG221SN1D
C125100nF
A-BC-D
A-DC-B
0
1
U24PI3PCIE3442TQFN40
12
34
56
7
89
1011
1213
14
15
16
17
18
1920
2122
2324
2526
27
28
2930
3132
3334
3536
37
38
3940
41
C0+C0-
A1+A1-
C1+C1-
SEL
A2+A2-
C2+C2-
A3+A3-
C3+
GND
C3-
VDD
GND
D3-D3+
B3-B3+
D2-D2+
B2-B2+
GND
VDD
D1-D1+
B1-B1+
D0-D0+
B0-B0+
GND
OE#
A0+A0-
GNDP
R1060R
C178 100nF
R7686r6
A-BC-D
A-DC-B
0
1
U19PI3PCIE3442TQFN40
12
34
56
7
89
1011
1213
14
15
16
17
18
1920
2122
2324
2526
27
28
2930
3132
3334
3536
37
38
3940
41
C0+C0-
A1+A1-
C1+C1-
SEL
A2+A2-
C2+C2-
A3+A3-
C3+
GND
C3-
VDD
GND
D3-D3+
B3-B3+
D2-D2+
B2-B2+
GND
VDD
D1-D1+
B1-B1+
D0-D0+
B0-B0+
GND
OE#
A0+A0-
GNDP
C174 100nF
R6986r6
C116100nF
R63 42r2
C111100nF
R82390R
R58127R
R1070R
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
<Doc> 1
EMC2-DP - PCIe Switch Power
C
8 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
V10 V10A
V10A
V10
V10
V25AV25
V25
V25
V25A
C1471uF
C1601nF
C1451nF
U21BPEX8606BA
C5C6
C8
C9C10C11
D4
D5D6
D7D8
D9D10
D11
E4
E5E6E7E8E9E10
E11
F5F6F7F8F9F10
G3
G4
G5G6G7G8G9G10
G11
G12
H3
H4
H5H6H7H8H9H10
H11 J5J6J7J8J9J10
M7
L7L8
K4K11
L5L6L9
L10
L4L11
K5K6K7K8K9K10
M5M6M9M10M11
C7L12L14M8N1
N12N11N10N9
P12P11P10P9
VSSVSS
VDD25A
VSSVSSVSS
VDD25
VDD10VDD10
VDD10AVDD10A
VDD10VDD10
VDD25
VDD10
VSSTVSSTVSSTVSSTVSSTVSST
VDD10
VSSTVSSTVSSTVSSTVSSTVSST
VDD25A
VDD10
VSSTVSSTVSSTVSSTVSSTVSST
VDD10
VDD25A
VSS
VDD10
VSSTVSSTVSSTVSSTVSSTVSST
VDD10 VSSTVSSTVSSTVSSTVSSTVSST
VDD25A
VDD10AVDD10A
VDD10VDD10VDD10VDD10VDD10VDD10
VDD25VDD25
VSSTVSSTVSSTVSSTVSSTVSST
VSSVSSVSSVSSVSS
N/CN/CN/CN/CN/C
N/CN/CN/CN/C
N/CN/CN/CN/C
C1371nF
C1571nF
C1261nF
C1291nF
L11BLM21PG221SN1D
C171100nF
C1611nF
C1351nF
C148100nF
C172100nF
C1551nF
C140100nF
L10BLM21PG221SN1D
C149100nF
C1281nF
C1541nF
C1561nF
C1671nF
C150100nF
C1341nF
C1421nF
C132100nF
C170100nF
C1521nF
C1661nF
C151100nF
C1531nF
C173100nF
C1581nF
C1641nF
C141100nF
C133100nF
C1301uF
C1361nF
C1631nF
C1431nF
C1651nF
C1691uF
C1621nF
C1311uF
C1681uF
C1461uF
C1391uF
C1441nF
C1271nF
C1591nF
C1381uF
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ERNI 254823
V12M
When the EMC2 is an add-in card there is
always a supply of +5 and +3v3 from the
1-bank or 3-bank connectors. When using the
1-bank connector, an external +12v source is
required.
When the EMC2 is a host board, then external
power must be supplied for +12v, +5v and
+3v3.
The +3v3 (or v33in) is sent to the Trenz
module and switched to provide v33out to
power EMC2 board devices.
The Trenz module also requires +5v for its
on-board DCDCs.
3Amps for
PCIe switch
V33out goes high when Trenz module has switched the
3.3v pass-thru on. Then Q2 turns on and the DCDC
ON/OFF goes low (negative logic variant). The PCIe
switch will then be powered up.
R22 = R23 * (2.5V/0.5V - 1)
R22/R23 = 4
R25 = R26 * (1.8V/0.5V - 1)
R25/R26 = 2.6
<Doc> 1
EMC2-DP - Power Supply
C
9 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
V25VCCAUX
V12PV5
V33V18
V33OUT
V33OUT
V33IN
+12V
V10V5
V33OUT
REG2MAX8556
123456
7891011
14
17
16 1213
ININININININ
OUTOUTOUTOUTOUT
GN
D
TA
BEN POKFB
R26150R
C5222uF10V 1206
C6110uF TantA
C5410uF TantA
C49100nF 25V
R2720k
R25390R
PWREXT1HEADER 5
12345
C48DNF/1206
Q52N70021
32
R93 20k
R22470R
DCDC1OKL-T/3-W12NC
1
2
3
4
5
6
7
8
9 10
1112
ON/OFF
Vin
GN
D
Vout
Sense
Trim
GN
D
NC
Seq/Trk PGOOD
NCNC
C5122uF 25V 1812
C50100nF 25V
C6010uF TantA
R23120R
C5310uF TantA
REG1MAX8556
123456
7891011
14
17
16 1213
ININININININ
OUTOUTOUTOUTOUT
GN
D
TA
BEN POKFB
R2414k45
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AutoShutdown Plus
<Doc> 1
EMC2-DP - RS232
C
10 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
TX2
RX1
TX3
RX2
TX1
RX3
RS232_TX1RS232_TX2RS232_TX3
RS232_RX1RS232_RX2RS232_RX3
V18
V33OUT
V33OUT
V33OUT
C65100nF
C64100nF
C62100nF
RS1HEADER 9
123456789
C63100nF
U6MAX3387E
1
3
4
5
7 21
14
24
18
11
2
6
22
23
9
810
1312
1716
2019
15
C1+
C1-
C2+
C2-
T1IN T1OUT
R1OUT
FORCEOFF
R1IN
FORCEON
V+
V-
GN
DV
CC
INVALID
T2INT3IN
R2OUTR3OUT
R2INR3IN
T2OUTT3OUT
VL
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAINBOARDSEIC
ADC0
ADC1
NC
No thermal pad.
SEIC_USB_ID
ON SEIC
<Doc> 1
EMC2-DP - SEIC
C
11 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
SATA_SEC_TX_NSATA_SEC_TX_P
SATA_SEC_RX_P
SATA_SEC_RX_N
SEIC_VBUS_V_EN
SEIC_OTG_D_NSEIC_OTG_D_P
AD1P
AD0P
AD0NAD0P AD1P
AD1N
SATA_SEC_TX_NSATA_SEC_TX_P
SATA_SEC_RX_NSATA_SEC_RX_P
AD1N
AD0N
SHIELD_USB
SEIC_OTG_D_N
SEIC_VBUS_V_EN
SEIC_VBUS
SEIC_OTG_D_P
SEIC_USB_D_PSEIC_USB_D_N
SEIC_VBUS
SEIC_USB_VBUS
tHDMI_D5tHDMI_D4tHDMI_D3
tHDMI_VSYNC
tHDMI_D2
tHDMI_HSYNC
tHDMI_D1
tHDMI_CLKtHDMI_DE
tHDMI_D11
tHDMI_INT
tHDMI_D10tHDMI_D9tHDMI_D8tHDMI_D7tHDMI_D6
tHDMI_D0
tPHY_MDI0_PtPHY_MDI0_NtPHY_MDI1_PtPHY_MDI1_N tPHY_MDI2_P
tPHY_MDI2_NtPHY_MDI3_PtPHY_MDI3_N
HDMI_D1
HDMI_CLK
PHY_MDI0_P
HDMI_DE
PHY_MDI0_NPHY_MDI1_PPHY_MDI1_N
HDMI_D5HDMI_D4HDMI_D3
HDMI_VSYNC
HDMI_D2
HDMI_D0
HDMI_HSYNC
HDMI_D11
HDMI_INT
HDMI_SCL
PHY_MDI2_P
HDMI_D10
PHY_MDI2_N
HDMI_D9
PHY_MDI3_P
HDMI_D8
PHY_MDI3_N
HDMI_D7
HDMI_SDA
HDMI_D6
tCEC_CLKtCT_HPDtLS_OE
CEC_CLKCT_HPDLS_OE
tAD0P tAD1PtAD0N tAD1N
SIN_PSIN_N
SOUT_PSOUT_N
OTG_D_POTG_D_N
VBUS_V_ENtSEIC_USB_ID
VBUS
SEIC_LEDT1LED4SEIC_LED4
SEIC_LED3 LEDT1SEIC_LEDT2
LED3LEDT2
PHY_LED2PHY_LED1SEIC_PHY_LED2SEIC_PHY_LED1
UART_RX UART_TXSEIC_UART_RX SEIC_UART_TX
SEIC_LED4
SEIC_LEDT1SEIC_LEDT2
SEIC_LED3
TSPDIFINTSPDIFOUT
I2C0_SDAI2C0_SCL
SPDIF_OUTSPDIF_IN
tSATA_SEC_TX_PtSATA_SEC_TX_N
tSATA_SEC_RX_PtSATA_SEC_RX_N
V18 V18 V18V18
V5 V5
V33IN V33IN
V33OUT V33OUT
V5
V33OUT
VCCIO34 VCCIO34tVCCIO34 tVCCIO34
R42 390R
A2Connector - MMCX
12345
SigGndGndGndGnd
R43 390R
J3LSHM-150
13579111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101
2468
101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698
100
102
13579
111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101
2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698100
102
L6BLM21PG221SN1D
R44 390R
J7
USB-A connector
1234
567
VBUSD-D+GND
SHSHSH
J4LSHM-150
13579111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101
2468
101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698
100
102
13579
111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101
2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698100
102
C8010uF 10V
R39 1k0
R45 390R
U10TPS2051D
1
23
4
5
678
9GND
ININ
EN
OC
OUTOUTOUT
GND
LED1WP914CK
12345678
12345678
C81100uF 10V
C79100nF
A1Connector - MMCX
12345
SigGndGndGndGnd
L5LINE_FILTER_WE_CNSW_HF
12
3 4
JP5HEADER 2
12
J1
SATA
1234567
JP4HEADER 3
123 R40 10k0
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
External clock input.
VCCIO35 (1.8V)
External clock input.
<Doc> 1
EMC2-DP - Clock
C
12 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
PPS1
CLK1
CLK2
CLK3
CLK4I2C0_SDAI2C0_SCL
CLK_PWR
VCCIO35
V33OUT
R30 0R
X125MHz Xtal
1
2
3
4
X1
GND
X2
GNDJ6Connector - MMCX Mounting Hole
12345
SigGndGndGndGnd
C7310uF
C70100nF
J5Connector - MMCX Mounting Hole
12345
SigGndGndGndGnd
C69100nF
C67100nF
R31 0R
R32 0R
C72100nF
U7SI5338A-B-GM
123456
7
8910
11
12
1314
1516
1718
19
20
2122
23
24
25
IN1IN2IN3IN4IN5IN6
VDD
INTRCLK3BCLK3A
VDDO3
SCL
CLK2BCLK2A
VDDO2VDDO1
CLK1BCLK1A
SDA
VDDO0
CLK0BCLK0A
RSVD_GND
VDD
PAD
C6622uF 6v3
R115 1k0
C71100nF
R29 0R
R28 10R
C68100nF
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GND
PCIe TX signals are host centric. So a TX pin on the PCIe connector means that
it goes to a TX pin on the host, and therefor the RX pin on the Trenz module.
The Trenz TX pin goes to the FMC C2M pin as the EMC2 is an FMC carrier.
The Trenz SATA TX goes to a switch which direct the signal to either a SATA
connector on the SEIC, or to the PCIe connector. Note that there cannot be a
PCIe host at the same time as this would want to drive the SATA.
Note that all LSHM pin-outs have left-right side swapping compared to the
Trenz modules. This is due to the LSHM hermaphroditic property.
NOSEQ
EN1
Hardwire 2-3
Hardwire 2-3
PGOOD
BOOTMODE
3v3
3v3
3v3
3v3
3v3
3v3
3v3
3v3
1v8
1v8
1v8
1v8
1v8
1v8
1v8
B12_L2_N
MIO0
MIO9
B12_L3_P
B12_L3_N
B12_L22_P
B12_L20_N
o/c pull-up
B12_L21_N
B12_L21_P
B12_L15_P
B12_L15_N
B35_L18_P
<Doc> 1
EMC2-DP - Trenz Module
C
13 13Tuesday, February 16, 2016
Title
Size Document Number Rev
Date: Sheet of
PHY_MDI0_P
PHY_MDI1_N
PHY_MDI2_PPHY_MDI2_N
PHY_MDI3_PPHY_MDI3_N
B12_L6_PB12_L6_NB12_L4_PB12_L4_N
B12_L7_PB12_L7_NB12_L8_PB12_L8_N
B12_L10_PB12_L10_NB12_L23_PB12_L23_N
B12_L14_NB12_L14_PB12_L24_NB12_L24_P
B12_L18_PB12_L18_N
B12_L12_P
MIO40
VBAT
B12_L19_P
MIO45
B12_L16_P
MIO44
B12_L19_N
B12_L11_N
B12_L16_N
B12_L1_P
MIO43
B12_L11_P
B12_L1_N
MIO42
B12_L9_PB12_L9_N
B12_L13_N
B12_L12_N
MIO41
B12_L13_P
B34_L23_PB34_L20_PB34_L23_N
B34_L21_NB34_L16_PB34_L16_N
B34_L22_N
B34_L10_PB34_L10_NB34_L22_P
VBUS_V_EN
OTG_D_POTG_D_NOTG_ID
USB_VBUSB34_L13_PB34_L13_N B34_L14_N
B34_L14_P
B35_L20_PB35_L20_N
B35_L22_NB35_L22_P
B35_L9_NB35_L9_P
B35_L24_PB35_L24_N
B35_L17_PB35_L17_N
B35_L2_NB35_L2_P
B35_L23_NB35_L23_P
B35_L12_PB35_L12_N
B34_L15_NB34_L15_PRESIN
B34_L21_PB34_L20_N
VCCIO13
PHY_MDI0_N
PHY_MDI1_P
VC
CIO
35
B35_L15_NB12_L2_P
B34_L2_P
B34_L6_PB34_L6_N
B35_L16_N
B35_L14_N
B35_L13_PB35_L13_N
B35_L14_P
B12_L5_PB12_L5_N
B12_L20_P
MODE
MIO15
SOUT_NSOUT_P SIN_P
SIN_N
B12_L22_N
MIO14JTAGEN
B35_L15_P
MIO13
B34_L2_N
B35_L16_P
VC
CIO
34
B35_L11_P
B35_L6_P
B34_L12_P
B35_L8_N
B34_L8_N
tAD0N
B34_L7_P
B35_L8_P
B35_L6_N
B34_L12_N
B35_L5_P
tAD1P
TDO
B35_L21_N
TMS
B35_L4_P
B35_L11_N
B34_L8_P
B35_L19_P
B34_L18_N
B34_L17_N
B34_L7_N
B35_L4_N
B35_L19_N
B35_L7_P
tAD0P
B35_L5_N
B34_L11_P
B35_L7_N
TDI
B34_L11_N
B34_L17_P
TCK
B34_L18_P
tAD1N
B35_L21_P
B35_L18_N
B35_L10_NB35_L10_P
B35_L25
B35_L0
MIO11MIO10
MIO12
B12_L17_PB12_L17_N
SD_D3SD_D2SD_D1SD_D0SD_CMDSD_CLK
tPHY_MDI3_PtPHY_MDI3_N
tPHY_MDI2_NtPHY_MDI2_P
tPHY_MDI0_PtPHY_MDI0_N
tPHY_MDI1_PtPHY_MDI1_N
tHDMI_D5 tHDMI_D4
tHDMI_DE
tHDMI_D7
tHDMI_D11
tHDMI_CLK
tHDMI_D3
tHDMI_D8
tHDMI_HSYNC
tHDMI_D9
tHDMI_VSYNC
tHDMI_D10
tHDMI_D2
tHDMI_D6
tHDMI_D1tHDMI_D0
TSPDIFOUTTSPDIFIN
VBAT
SD_SW
PE1RXP0
PE1RXP3
PE1RXN0
PE1TXN3PE1TXP3
PE1RXN3
RS232_TX1RS232_TX2RS232_TX3
RS232_RX2RS232_RX3
PE1TXN0PE1TXP0
VBUS_V_ENVBUS
OTG_D_POTG_D_N
tSEIC_USB_ID
tFMC_TRZ_CK_NtFMC_TRZ_CK_P
RS232_RX1
UART_TX
UART_RX
LED1
LED2
PCIeRST18#
CLK4CLK3
CLK1CLK2
TDI
TTL2
tAD1N
tAD0P
PPS1
TTLP
TDO
TTLN
TTL0TTL1
TTL3
TCK
TMS
WIRE1
tLS_OE
tAD1P
tCT_HPD
tCEC_CLK
tHDMI_INT
tAD0N
TRENZRST#
PHY_LED1PHY_LED2
HOST#
I2C1_SDAI2C1_SCL
I2C0_SCLI2C0_SDA
SIN_NSIN_P
SOUT_NSOUT_P
RTC_INT#
tFMC_LA10_PtFMC_LA10_N
tFMC_LA06_NtFMC_LA06_P
tFMC_LA26_NtFMC_LA26_P
tFMC_LA05_NtFMC_LA05_P
tFMC_LA25_NtFMC_LA25_P
tFMC_LA20_NtFMC_LA20_P
tFMC_LA08_NtFMC_LA08_P
tFMC_LA03_PtFMC_LA03_N
tFMC_LA32_N
tFMC_LA32_P
tFMC_LA19_NtFMC_LA19_P
tFMC_LA15_NtFMC_LA15_P
tFMC_LA07_PtFMC_LA07_N
tFMC_LA04_NtFMC_LA04_P
tFMC_LA02_PtFMC_LA02_N
tFMC_LA13_P
SATA_TRZ_TX_PSATA_TRZ_TX_N
SATA_TRZ_RX_PSATA_TRZ_RX_N
tFMC_TRZ_RX_PtFMC_TRZ_TX_PtFMC_TRZ_TX_N tFMC_TRZ_RX_N
PCLKP0PCLKN0
FMC_SDAFMC_SCL
PRSNT_M2C_L
tFMC_LA17_NtFMC_LA17_P
tFMC_LA18_PtFMC_LA18_N
tFMC_CLK1_NtFMC_CLK1_P
tFMC_LA23_PtFMC_LA23_N
tFMC_LA12_NtFMC_LA12_P
tFMC_LA11_NtFMC_LA11_P
tFMC_LA13_N
tFMC_CLK0_NtFMC_CLK0_P
tFMC_LA00_NtFMC_LA00_P
tFMC_LA01_PtFMC_LA01_N
tFMC_LA09_NtFMC_LA09_P
tFMC_LA14_NtFMC_LA14_P
tFMC_LA21_PtFMC_LA21_N
tFMC_LA22_NtFMC_LA22_P
tFMC_LA24_NtFMC_LA24_P
tFMC_LA27_PtFMC_LA27_N
tFMC_LA28_NtFMC_LA28_P
tFMC_LA29_PtFMC_LA29_N
tFMC_LA30_NtFMC_LA30_P
tFMC_LA31_PtFMC_LA31_N
tFMC_LA33_NtFMC_LA33_P
tFMC_LA16_NtFMC_LA16_P
V33IN
VIOB
V33OUT
V33OUT
V18
V33OUT
V18
V5 V5
VCCJTAG
VCCIO35
VCCIO34
VCCIO35
V33OUT
V25
V25
V33IN
V33IN
R954k7
JB2
LSHM-150
13579
111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101
2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698100
102
13579111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101
2468
101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698
100
102
JP7HEADER 3
123
R48DUALR4k7
JP8HEADER 3
123
JP11HEADER 3
123
R94 0R
C82100nF 50V
R964k7
R116 0R
R974k7
C83100nF 50V
JP7AHEADER 1
1
R984k7
JB1
LSHM-150
13579
111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101
2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698100
102
13579111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101
2468
101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698
100
102
JB3
LSHM-130
1357911131517192123252729313335373941434547495153555759
61
2468
1012141618202224262830323436384042444648505254565860
62
13579
11131517192123252729313335373941434547495153555759
61
24681012141618202224262830323436384042444648505254565860
62
R92 4k7
JP8AHEADER 1
1
© 2017 Sundance Multiprocessor Technology Ltd.This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.Please see the CERN OHL v. 1.2. for applicable conditions.