© 2003 Fast-Chip. All rights reserved. 04/20/23 07:17 PM
RTL-SynchronizedTransaction Reference Models
Dave Whipp
Fast-Chip Inc.
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Motivation
›Needed Cycle Verification•Now, not 6 months later
›Why build two models, when one will do•We had a working “functional” model
›Don’t Chase RTL•Avoid modeling artifacts of the implementation
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Overview
1. What is Transaction Synchronization
2. Patterns in Transaction Synchronization
3. Methodology, Futures, Summary
© 2003 Fast-Chip. All rights reserved. 04/20/23 07:17 PM
Part 1
What is Transaction Synchronization?
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A Functional Model
int classify_packet ( Packet packet_data, Uint32 rule_address ){
int result = ITERATE while (result == ITERATE) {
RuleStruct rule; read_rule(&rule, rule_address); int field = extract(rule, packet_data); interpret(rule, field, &result, &rule_address);
} return result;
}
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“Bringup” Flow
test.script C-sim
RTL-sim
Compare
csim.log
rtl.log
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Transaction Interactions
Read-Rule
Rules DB
Write-Rule
Thread A Thread B
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Trace Files
›A trace of the sequence of transaction steps›Each synch point has a name, and thread-ID
•Comments provide context (values from RTL)
›Often hand-edited during debug
Example:[1536] read_rule thread_A # addr=h8a34 data=h1578[1544] write_rule thread_B # addr=h8a34 data=h5343[1632] read_rule thread_A # addr=h8a34 data=h5343[1694] write_rule thread_B # addr=h8a34 data=hf519[1694] read_rule thread_A # addr=h8a34 data=hf519
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“Synchronized” Flow
C-sim
RTL-sim
Compare
csim.log
rtl.logtest.script
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Simulation Kernel
Read Synch
Read Stimulus
[pending]
[not pending]
Call Synchfunction
Pending SynchPoints (task list)
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Memory Access with Arbiter
A
B
Arb Mem
Monitor
Delay Delay
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Dual Port Memory Access
Monitor A Monitor B
A BMemoryDelay Delay
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int field = extract(rule, packet_data); interpret(rule, field, &result, &rule_address);
}return result;
}
A Functional Model
}
int continue_read_rule (){
int classify_packet ( Packet packet_data, Uint32 rule_address ){
int result = ITERATEwhile (result == ITERATE){
RuleStruct rule; read_rule(&rule, rule_address);
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Refactoring
1. Move local variables into a “context” structure. Create an instance (on the heap, not the stack) at start of transaction – and delete at end.
2. Replace iterative loops with recursive functions.
3. For each function that requires synchronization (directly or indirectly), replace the call with a request/callback pair.
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
“Context” Structure
struct context{
Packet packet_data;Uint32 rule_address;RuleStruct rule;int field;int result;
void (*callback) (int);};
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Introduce Context Structure
void classify_packet_request (Packet packet_data, Uint32 rule_address, void (*callback)(int))
{ struct context *cxt = calloc(1, sizeof(struct context)); cxt->packet_data = packet_data; cxt->rule_address = rule_address; cxt->callback = callback;
cxt->result = ITERATE;
classify_packet_iterate(cxt);}
void packet_classify_reply(struct context *cxt){
int result = cxt->result;void (*callback)(int) = cxt->callback;free(cxt);callback(result);
}
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Non-Recursive Implementation
void classify_packet_iterate ( struct context *cxt )
{
while (cxt->result == ITERATE)
{
read_rule(&cxt->rule, cxt->rule_address);
cxt->field = extract(cxt->rule, cxt->packet_data);
interpret(cxt->rule, cxt->field, &cxt->result, &cxt->rule_address);
}
classify_packet_reply(cxt);
}
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Recursive Implementation
void classify_packet_iterate ( struct context *cxt )
{
if (cxt->result == ITERATE)
{
read_rule(&cxt->rule, cxt->rule_address);
cxt->field = extract(cxt->rule, cxt->packet_data);
interpret(cxt->rule, cxt->field, &cxt->result, &cxt->rule_address);
classify_packet_iterate(cxt);
}
else
{
classify_packet_reply(cxt);
}
}
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Synchronized Implementation
void classify_packet_iterate ( struct context *cxt ){
if (cxt->result == ITERATE) {
read_rule_request(&cxt->rule, cxt->rule_address, &classify_packet_continue); } else {
classify_packet_reply(cxt); }
}
void continue_read_rule ( struct context *cxt ){ cxt->field = extract(cxt->rule, cxt->packet_data); interpret(cxt->rule, cxt->field, &cxt->result, &cxt->rule_address); classify_packet_iterate(cxt);}
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Transaction Diagrams
Extract
Interpret
Read Rule
[done] [iterate]
Rules DB
Packet Buffer
Classify Packet
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Part 2
Patterns in Transaction Synchronization
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Adding a Cache
›Cache needn’t effect transactions•Data-RAM not modeled
•cache is coherent
•Can rerun all tests, with no changes to C model
›Tag RAM is an Addition, not Modification•Independent Transactions
•Independent Synchronization
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Single Port, Cached
A
B
Arb Mem
Read/Write
Delay DelayCache
Tag RAMMiss Rd/Wr
Hit Rd/Wr
Correct Errors
Check ECC
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Cache Transaction (Read)
Read Data
[hit]
Write Tag
Read Tag
Read Tag
[miss]
Write TagCheck ECC
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FIFOs and Counters
›Delay elements need no synchronization•But synchronization can increase locality
›Some FIFOs can drop transactions•Synchronize overflow: don’t model actual size
›Counters seem to need cycle-based model•We want to avoid this
›Correct Synch propagates “forces” to Model
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Force
Synchronizing a FIFO
Flow Control
Producer ConsumerFIFO
Push Pop
Drop
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FIFO Transaction Diagram
[drop]
[push]
Pop
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FIFO Synchronization Checker
Producer ConsumerFIFO
Push PopDrop
Checker: Queue Size Assertions
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Force
value
Counters
Register+1
load
Client
UpdateSample
value
select clk sample_en
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Scaffolding
›Permit verification incomplete RTL•Encourage end-to-end skeletons
•Implement “incorrect, but simple” algorithms•Don’t wait for complete RTL
•Postpone modeling the algorithm
•Use synch to avoid chasing a moving target
•Remove scaffolding once RTL is complete
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
An Algorithm Cache
Read Node
TreeSearch
NodeMemory
Result Cache
Hit Miss
Tag Ram
Hit Rd/Wr
Miss Rd/Wr
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Algorithm Cache: Transactions
Read Node
[match]
[No match]
[iterate]
[hit]
[miss]
Backdoorsearch
Read Tag
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Speculation
›When hardware speculates:•Effect precedes cause
•Transaction model appears incorrect
›Creative accounting can sometimes help•Insert a “virtual” delay
•Filter based on future events
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Speculation
Read Ctrl
Read Data
Read Data
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Speculation
Read Ctrl
Read Data
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Speculative Reads
Stage 1 Stage 2 Stage 4Stage 3
Ctrl RAMUpdate
Lookup(Pipe)
write
read
Delay (2 clocks)?
write
read
Data RAMUpdate
advance (2 clocks)?
© 2003 Fast-Chip. All rights reserved. 04/20/23 07:17 PM
Part 3
Methodology, Futures, Summary
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Verification Flow
›RTL Simulation is expensive•Licenses
•CPU time
›Post-Processing is cheap
›Stop simulations when broken•But not if bug is in test/model
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Methodology
›Cycle-Precise Reference Comparison•Without a cycle-accurate model
›Verify the System First•Bringup Flow (Function Model)
•Synchronized Flow (Transaction-Testbench)
›Postpone module level testing•Use scoreboarding to identify unit testbenches
•Only build unit-testbenches for stable modules
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Comparison with Platform-Based
›System-on-Chip Methodology•Verify components first
•Verify system as composition of verified units
›Complex-ASIC Methodology•Verify transactions first
•Verify units in context of verified transactions
•An “Agile” Methodology
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Future Work
›Performance in non-synchronized mode•Use threading to avoid fragmentation
›Synchronization as basis of SW architecture•Cycle-model plug-in could provide synch
•Can postpone this plug-in until tapeout
›But what if we want a cycle-model earlier?•Example: up-front performance validation
© 2003 Fast-Chip Confidential. All rights reserved. 04/20/23 07:17 PM
Summay
›Cycle timing is a “Don’t Care”
› Initial verification uses “Functional” model•Refactor into “Transaction” model
›RTL provides cycle timing•Caches, like FIFOs, are just delay elements
•“Forces” in testbench propagate to model
›“Coarse-grain first” methodology
© 2003 Fast-Chip. All rights reserved. 04/20/23 07:17 PM
Questions
mailto:[email protected]
http://Dave.Whipp.name/dv