Top Banner

Click here to load reader

vcs mx user guide - University of · PDF file 2014. 4. 10. · VCS® MX/VCS MXi™ User Guide Version D-2010.06 June 2010 Comments? E-mail your comments about this manual to:...

Aug 05, 2021

ReportDownload

Documents

others

vcs_mx_user_guide.bookCopyright Notice and Proprietary Information Copyright © 2010 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.
Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page:
This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of
_________________________________ and its employees. This is copy number______.”
Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them.
Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Registered Trademarks (®) Synopsys, AMPS, Cadabra, CATS, CRITIC, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM, HSPICE, iN-Phase, in-Sync, Leda, MAST, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PrimeTime, SiVL, SNUG, SolvNet, System Compiler, TetraMAX, VCS, Vera, and YIELDirector are registered trademarks of Synopsys, Inc.
Trademarks (™) AFGen, Apollo, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, Columbia, Columbia-CE, Cosmos, CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision, DesignerHDL, Direct Silicon Access, Discovery, Encore, Galaxy, HANEX, HDL Compiler, Hercules, Hierarchical Optimization Technology, HSIMplus, HSPICE-Link, iN-Tandem, i-Virtual Stepper, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Magellan, Mars, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, Planet, Planet-PL, Polaris, Power Compiler, Raphael, Raphael-NES, Saturn, Scirocco, Scirocco-i, Star-RCXT, Star-SimXT, Taurus, TSUPREM-4, VCS Express, VCSi, VHDL Compiler, VirSim, and VMC are trademarks of Synopsys, Inc.
Service Marks (SM) MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.
SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. All other product or company names may be trademarks of their respective owners.
iii
Contents
VCS MX Support with Technologies . . . . . . . . . . . . . . . . . . . . . . 1-2
Setting Up VCS MX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Verifying Your System Configuration . . . . . . . . . . . . . . . . . . . 1-4 Obtaining a License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Setting Up Your Environment. . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Setting Up Your C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Creating a synopsys_sim.setup File . . . . . . . . . . . . . . . . . . . 1-9
The Concept of a Library In VCS MX. . . . . . . . . . . . . . . . 1-11 Library Name Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Including Other Setup Files . . . . . . . . . . . . . . . . . . . . . . . 1-12 Using SYNOPSYS_SIM_SETUP Environment Variable . 1-13
Displaying Setup Information. . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Displaying Design Information Analyzed Into a Library . . . . . 1-14
Using VCS MX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Basic Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Default Time Unit and Time Precision . . . . . . . . . . . . . . . . . . . . . 1-18
iv
Commonly Used Analysis Options . . . . . . . . . . . . . . . . . . 2-3 Using vlogan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Commonly Used Analysis Options . . . . . . . . . . . . . . . . . . 2-6 Analyzing the Design to Different Libraries . . . . . . . . . . . . . . 2-13
Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Using vcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Commonly Used Options . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Interactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Commonly Used Runtime Options. . . . . . . . . . . . . . . . . . . . . 2-19
3. Elaborating the Design
Key Elaboration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Initializing Verilog Memories and Registers . . . . . . . . . . . . . . 3-3
Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Overriding Generics and Parameters . . . . . . . . . . . . . . . . . . 3-6
Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Checking for X and Z Values In Conditional Expressions . . . 3-8
v
Enabling the Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Filtering Out False Negatives . . . . . . . . . . . . . . . . . . . . . . 3-10
Cross Module References (XMRs) . . . . . . . . . . . . . . . . . . . . 3-12 hdl_xmr Procedure and $hdl_xmr System Task. . . . . . . . 3-13 Data Types Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 VHDL Referencing Verilog using hdl_xmr procedure. . . . 3-14 Verilog Referencing VHDL objects using $hdl_xmr . . . . . 3-16 Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 $hdl_xmr Support for VHDL Variables . . . . . . . . . . . . . . . 3-18 Datatype Support and Usage Examples . . . . . . . . . . . . . 3-19
VCS MX V2K Configurations and Libmaps . . . . . . . . . . . . . . 3-24 Library Mapping Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Using +evalorder Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
4. Simulating the Design
Options for Debugging Using DVE and UCLI . . . . . . . . . . . . . . . 4-6
Key Runtime Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Overriding Generics at Runtime. . . . . . . . . . . . . . . . . . . . . . . 4-8
Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Passing Values from the Runtime Command Line . . . . . . . . 4-13
vi
5. VCS Multicore Technology Application Level Parallelism
VCS Multicore Technology Options. . . . . . . . . . . . . . . . . . . . . . . 5-16 Use Model for Assertion Simulation. . . . . . . . . . . . . . . . . . . . 5-18 Use Model for Toggle and Functional Coverage . . . . . . . . . . 5-18 Use Model for VPD Dumping. . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Running VCS Multicore Simulation . . . . . . . . . . . . . . . . . . . . . . . 5-19 Assertion Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Toggle Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 VPD File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Parallel SAIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Customary SAIF System Function Entries. . . . . . . . . . . . . . . 5-24 Enabling Parallel SAIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
6. VPD, VCD, and EVCD Utilities
Advantages of VPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Enable and Disable Dumping. . . . . . . . . . . . . . . . . . . . . . 6-4 Override the VPD Filename . . . . . . . . . . . . . . . . . . . . . . . 6-8 Dump Multi-dimensional Arrays and Memories . . . . . . . . 6-9 Using $vcdplusmemorydump . . . . . . . . . . . . . . . . . . . . . . 6-20 Capture Delta Cycle Information . . . . . . . . . . . . . . . . . . . 6-20
Dumping an EVCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
vii
Options for specifying EVCD options . . . . . . . . . . . . . . . . 6-26 The vpd2vcd Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
The Command File Syntax. . . . . . . . . . . . . . . . . . . . . . . . 6-34 The vpdmerge Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
7. Performance Tuning
Compile-time Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Compile Once and Run Many Times . . . . . . . . . . . . . . . . . . . 7-4 Parallel Compilation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Runtime Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Using Radiant Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Compiling With Radiant Technology. . . . . . . . . . . . . . . . . 7-6 Applying Radiant Technology to Parts of the Design . . . . 7-6
Improving Performance When Using PLIs. . . . . . . . . . . . . . . 7-16 Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Impact on Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
8. Gate-level Simulation
SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Using Unified SDF Feature . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Using $sdf_annotate System Task. . . . . . . . . . . . . . . . . . . . . 8-3
Delays and Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Transport and Inertial Delays. . . . . . . . .…