TAPIS PELEWAT JALUR MENGGUNAKAN KAPASITOR TERSAKLAR TUGAS AKHIR Diajukan untuk memenuhi salah satu syarat Memperoleh gelar Sarjana Teknik Program Studi Teknik Elektro Disusun oleh : Noviyanti Maya Dewi Kia NIM : 995114071 JURUSAN TEKNIK ELEKTRO FAKULTAS TEKNIK UNIVERSITAS SANATA DHARMA YOGYAKARTA 2007 i
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TAPIS PELEWAT JALUR MENGGUNAKAN KAPASITOR TERSAKLAR
TUGAS AKHIR
Diajukan untuk memenuhi salah satu syarat Memperoleh gelar Sarjana Teknik
Program Studi Teknik Elektro
Disusun oleh :
Noviyanti Maya Dewi Kia
NIM : 995114071
JURUSAN TEKNIK ELEKTRO FAKULTAS TEKNIK
UNIVERSITAS SANATA DHARMA YOGYAKARTA
2007
i
Halaman Persembahan
YESUS………..
DIA tidak pernah berjanji…. langit cerah tanpa hujan, Hidup suka tanpa duka,
Bunga mekar tanpa layu, Wajah tersenyum tanpa air mata,
Tapi DIA berjanji, Akan menyertai mu hingga akhir jaman……
Seperti Ia telah menyertaiku,dalam setiap denyut nadiku
BUBY……buby……… THX dah nemenin selama di jogja………..
LOVE U BUBY……….huk….huk…huk…
…
TAPIS PELEWAT JALUR MENGGUNAKAN KAPASITOR
TERSAKLAR
NAMA : NOVIYANTI MAYA DEWI KIA
NIM : 995114071
INTISARI
Berawal dari semakin berkembangnya teknologi khususnya teknologi telekomunikasi, antara lain telepon, radio, dan berbagai alat elektronika yang semuanya menggunakan penepis (filter) untuk membatasi arus listrik dengan frekuensi-frekuensi tertentu, sesuai dengan yang dibutuhkan, maka dibuatlah sebuah penepis aktif dengan menggunakan kapasitor tersaklar Penelitian ini bertujuan untuk lebih memahami dasar-dasar tapis pelewat jalur, system ordo frekuensi cutoff, tanggapan frekuensi, dan kapasitor tersaklar. Frekuensi tengah yang digunakan adalah 4000 Hz dengan frekeunsi clock-nya adalah 150 KHz.
vii
BANDPASS SWITCHED CAPACITOR FILTER
NAME : NOVIYANTI MAYA DEWI KIA
NIM : 995114071
ABSTRACT
Early from progressively expand technological on specially telecommunication technology, for example telephone, radio, and various all electronic appliance, filter is used to limit the electrics current with the certain frequency that is required. So that is needed to design an active filter using switch capacitor.
The objective of this research is to get deeper understanding about the bandpass filter, system order, cutoff frequency, frequency response, and switch capacitor.Cutoff frequency for bandpass filter is design about 4000 Hz with clock frequency is used is 150 KHz.
viii
KATA PENGANTAR
Puji kehadirat Tuhan yang Maha Esa, Tuhanku Yesus Kristus yang telah
memberikan rahmat dan berkat-NYA, sehingga penyususn dapat menyelesaikan tugas
akhir ini.
Atas tersusunnya tugas akhir ini, penyususn mengucapkan banyak terima kasih
kepada:
1. Bapak Agustinus Bayu Prinawan,S.T., M.Eng, selaku Ketua Jurusan Teknik
Elektro Fakultas Teknik Universitas Sanata Dharma Yogyakarta.
2. Bapak Martanto, S.T, M.T, selaku Dosen Pembimbing I yang telah meluangkan
waktu guna memberikan bimbingan,saran dan kritik.
3. Orang tuaku tercinta, papi dan mami,yang telah memberikan do’a, kasih sayang,
pengertian, dan semangat.
4. Pak Pur dan Mama Irna, terima kasih untuk do’a, dan kasih sayangnya.
5. Kakakku Tony, adek Yola, my lovely Rio, terima kasih atas bantuan dan
dorongannya, ‘n BUBY……(thx dah nemenin selama di jogja, dan menghibur
dengan gonggongan-mu….huk…huk…)
6. Mas Wawan, terima kasih atas doa, perhatian, dan sayangnya ,hingga tugas akhir
ini selesai. ( you best I ever had).
7. Semua temen kos, Sitha.Ira, Mbk Ayu,(kalian teman yang menggilakan, tapi juga
menyenangkan) ‘n rekan mahasiswa Santi, Roy, Dagul, Tutus, Ari Inyonk, Anci’,
Oscar, Giri, Dini, Bledex, Nica Ebensina, dan semua temen TE’99,
Atas, ( c) Tapis Pelewat Jalur dan (d) Tapis Penolak Jalur
Empat macam tapis dapat dijelaskan sebagai berikut :
1. Tapis Pelewat Rendah (Low Pass Filter) adalah tapis yang memiliki jalur
pelewat dari ω=0 sampai ω=ωo, dengan ωo disebut sebagai frekuensi pancung
(cut off frequency).
2. Tapis Pelewat Tinggi (High Pass Filter) merupakan komplomen dari tapis
pelewat rendah, dengan frekuensi dari 0 sampai ωo merupakan jalur henti (stop
band), sedangkan jalur pelewat adalah dari frekuensi ωo sampai tak hingga.
3. Tapis Pelewat Jalur (Band Pass Filter) adalah tapis yang melewatkan frekuensi
antara ω1 sampai ω2, selain frekuensi ini tidak dilewatkan.
4. Tapis Jalur Henti (Band Elimination Filtar) merupakan komplemen dari Tapis
Pelewat Jalur dengan frekuensi dari ω1 sampai ω2 dihentikan dan lainnya
dilewatkan. Tapis ini sering dinamakan ‘notch filter’.
Watak tapis yang nyata yang berhubungan dengan keempat macam tapis
ditunjukan pada Gambar 2-2. Watak pelemahan yang berhubungan dengan Gambar
2-2 ditunjukkan pada Gambar 2-3. Hubungan kedua besaran ini ditunjukkan pada
persamaan 2-1.
| T | | T |
(b)
ο (a) ω ο ω
| T | | T | ο ( c ) ω ο ω (d) Gambar 2-2. Tanggapan tapis nyata. (a) Tapis Pelewat Rendah,(b) Tapis Pelewat Atas,(c) Tapis Pelewat Jalur dan (d) Tapis Penolak Jalur.
α α
ο (a) ω ο (b) ω α α ο (c) ω ο (d) ω
Gambar 2-3. Watak pelemahan tapis yang berhubungan dengan gambar 2-2. (a)
A (f) = 20 log (Vo / Vi) At (f) = 20 log [T1 (f) * T2(f)]
4.3 Karakteristik Tapis Pelewat Jalur dengan Kapasitor Tersaklar
Untuk mengetahui kebenaran dari tapis pelewat jalur yang telah dibuat yang
dibandingkan dengan watak tapis pelewat jalur perancangan, maka dari watak yang telah
digambarkan perlu diketahui beberapa hal antara lain, dicari lebar pita pelewat dan
frekuensi pusat pelewat.
Frekuensi pusat pada tapis pelewat jalur merupakan frekuensi dengan penguatan
yang paling besar atau penguatan pada puncak kurva tanggapan frekuensi tapis pelewat
jalur. Dalam hasil pengamatan, penguatan maksimal sebesar -6,0206 dB yang terdapat
pada frekuensi 3900 Hz.
Lebar jalur pelewat pada BPF dapat ditentukan dengan mencari frekuensi
setengah daya (frekeunsi 3 – dB) pada kedua sisi peralihan tapis. Bila frekensi 3 – dB
yang berada di atas frekuensi pusat dinyatakan dengan hff =02 dan frekuensi 3 – dB
yang berada di bawah frekuensi pusat dinyatakan dengan lff =01 , maka lebar pelewat
dinyatakan sebagai
34
BW = 0102 ff −
4.3.1. Hubungan Frekuensi penyaklaran dengan tanggapan frekuensi
Untuk mengetahui pengaruh frekuensi penyaklar terhadap tanggapan frekuensi
dari Butterworth dengan kapasitor tersaklar, dilakukan pengamatan terhadap frekuensi
pusat.
Besar frekuensi pusat pada tapis pelewat jalur dinyatakan sebagai :
oϖ = C
Fclk ).( 21 RR CC
dengan
oω = 2π Fo, maka
Fo = C
Fclk.2π
).( 21 RR CC
Dengan nilai kapasitor-kapasitor C, , dan yang sudah tertentu, maka hubungan
Fo terhadap Fclk adalah linier. Dari sini terlihat bahwa bila Fclk naik maka Fo akan naik
dan sebaliknya.
1RC 2RC
BAB V
PENUTUP
Tapis dalam pengolahan isyarat listrik memiliki arti mengambil suatu komponen
frekuensi tertentu dari suatu isyarat dan menolak komponen frekuensi lain.
Tapis Butterwoth adalah tapis yang memiliki tanggapan datar secara meksimal
pada jalur pelewat. Sebuah hambatan dapat diganti dengan menggunakan kapasitor
tersaklar yang dinyatakan dengan Req = RclkCF
1 dengan adalah frekuensi clock dan
adalah kapasitor tersaklar dan Req adalah resistansi.
clkf
RC
Perancangan tapis Butterworth dengan menggunakan kapasitor tersaklar bias
dilakukan dengan terlebih dulu merancang untai analognya dan kemudian merealisasikan
kedalam untai yang memakai kapasitor tersaklar, dengan menggantikan resistor dengan
kapasitor tersaklar.
Untai keempat jenis tapis Butterworth dengan menggunakan kapasitor tersaklar
yang telah direalisasikan dengan frekuensi penyaklar 150 KHz. Untuk BPF fo = 400 Hz,
f = 3123,1056 Hz, f = 5123,1056 Hz, dan BW = 2 KHz. 01 02
Beberapa hal yang dapat menyebabkan kesalahan watak tapis hasil perancangan
jika dibandingkan dengan perhitungan antara lain : sifat-sifat dari komponen pembangun
untai tapis, dan adanya pendekatan yang diterapkan pada perhitungan saat perancangan.
DAFTAR PUSTAKA
• Eko Putranto, Afgianto, Penapis Aktif Elektronika : teori dan Praktek,
C.V. Gava Media Yogyakarta
• Franco, S., Design with Operational Amplifier and Analog Integrated
Circuit, Mc Graww Hill Book Co., Singapore, 1988.
• Parker, S P., Mc Graw Hill Concise Encyclopedia of Science and
Technology, Mc Graw Hill, Inc., New York, 1984.
• Http://www.yahoo.com
• Http://www.Panorama.net
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LF353Wide Bandwidth Dual JFET Input Operational AmplifierGeneral DescriptionThese devices are low cost, high speed, dual JFET inputoperational amplifiers with an internally trimmed input offsetvoltage (BI-FET II™ technology). They require low supplycurrent yet maintain a large gain bandwidth product and fastslew rate. In addition, well matched high voltage JFET inputdevices provide very low input bias and offset currents. TheLF353 is pin compatible with the standard LM1558 allowingdesigners to immediately upgrade the overall performance ofexisting LM1558 and LM358 designs.
These amplifiers may be used in applications such as highspeed integrators, fast D/A converters, sample and holdcircuits and many other circuits requiring low input offsetvoltage, low input bias current, high input impedance, highslew rate and wide bandwidth. The devices also exhibit lownoise and offset voltage drift.
Featuresn Internally trimmed offset voltage: 10 mVn Low input bias current: 50pAn Low input noise voltage: 25 nV/√Hzn Low input noise current: 0.01 pA/√Hzn Wide gain bandwidth: 4 MHzn High slew rate: 13 V/µsn Low supply current: 3.6 mAn High input impedance: 1012Ωn Low total harmonic distortion : ≤0.02%n Low 1/f noise corner: 50 Hzn Fast settling time to 0.01%: 2 µs
Typical Connection
00564914
Simplified Schematic1/2 Dual
00564916
Connection DiagramDual-In-Line Package
00564917
Top ViewOrder Number LF353M, LF353MX or LF353N
See NS Package Number M08A or N08E
BI-FET II™ is a trademark of National Semiconductor Corporation.
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage ±18V
Power Dissipation (Note 2)
Operating Temperature Range 0˚C to +70˚C
Tj(MAX) 150˚C
Differential Input Voltage ±30V
Input Voltage Range (Note 3) ±15V
Output Short Circuit Duration Continuous
Storage Temperature Range −65˚C to +150˚C
Lead Temp. (Soldering, 10 sec.) 260˚C
Soldering InformationDual-In-Line Package
Soldering (10 sec.) 260˚C
Small Outline Package
Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C
See AN-450 “Surface Mounting Methods and Their Effecton Product Reliability” for other methods of solderingsurface mount devices.
ESD Tolerance (Note 8) 1000V
θJA M Package TBD
Note 1: Absolute Maximum Ratings indicate limits beyond which damage tothe device may occur. Operating ratings indicate conditions for which thedevice is functional, but do not guarantee specific performance limits. Elec-trical Characteristics state DC and AC electrical specifications under particu-lar test conditions which guarantee specific performance limits. This assumesthat the device is within the Operating Ratings. Specifications are not guar-anteed for parameters where no limit is given, however, the typical value is agood indication of device performance.
DC Electrical Characteristics(Note 5)
Symbol Parameter Conditions LF353 Units
MIn Typ Max
VOS Input Offset Voltage RS=10kΩ, TA=25˚C 5 10 mV
Over Temperature 13 mV
∆VOS/∆T Average TC of Input Offset Voltage RS=10 kΩ 10 µV/˚C
IOS Input Offset Current Tj=25˚C, (Notes 5, 6) 25 100 pA
Tj≤70˚C 4 nA
IB Input Bias Current Tj=25˚C, (Notes 5, 6) 50 200 pA
Tj≤70˚C 8 nA
RIN Input Resistance Tj=25˚C 1012 ΩAVOL Large Signal Voltage Gain VS=±15V, TA=25˚C 25 100 V/mV
VO=±10V, RL=2 kΩOver Temperature 15 V/mV
VO Output Voltage Swing VS=±15V, RL=10kΩ ±12 ±13.5 V
VCM Input Common-Mode Voltage VS=±15V ±11 +15 V
Range −12 V
CMRR Common-Mode Rejection Ratio RS≤ 10kΩ 70 100 dB
PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB
IS Supply Current 3.6 6.5 mA
AC Electrical Characteristics(Note 5)
Symbol Parameter Conditions LF353 Units
Min Typ Max
Amplifier to Amplifier Coupling TA=25˚C, f=1 Hz−20 kHz −120 dB
(Input Referred)
SR Slew Rate VS=±15V, TA=25˚C 8.0 13 V/µs
GBW Gain Bandwidth Product VS=±15V, TA=25˚C 2.7 4 MHz
en Equivalent Input Noise Voltage TA=25˚C, RS=100Ω, 16
f=1000 Hz
in Equivalent Input Noise Current Tj=25˚C, f=1000 Hz 0.01
LF35
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AC Electrical Characteristics (Continued)(Note 5)
Symbol Parameter Conditions LF353 Units
Min Typ Max
THD Total Harmonic Distortion AV=+10, RL=10k,VO=20Vp−p,BW=20 Hz-20 kHz
<0.02 %
Note 2: For operating at elevated temperatures, the device must be derated based on a thermal resistance of 115˚C/W typ junction to ambient for the N package,and 158˚C/W typ junction to ambient for the H package.
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: The power dissipation limit, however, cannot be exceeded.
Note 5: These specifications apply for VS=±15V and 0˚C≤TA≤+70˚C. VOS, IBand IOS are measured at VCM=0.
Note 6: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, Tj. Due to the limitedproduction test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambienttemperature as a result of internal power dissipation, PD. Tj=TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink isrecommended if input bias current is to be kept to a minimum.
Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS= ±6V to ±15V.
Note 8: Human body model, 1.5 kΩ in series with 100 pF.
Typical Performance CharacteristicsInput Bias Current Input Bias Current
0056491800564919
Supply Current Positive Common-Mode Input Voltage Limit
0056492000564921
LF353
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Typical Performance Characteristics (Continued)
Negative Common-Mode Input Voltage Limit Positive Current Limit
00564922 00564923
Negative Current Limit Voltage Swing
00564924 00564925
Output Voltage Swing Gain Bandwidth
00564926 00564927
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Typical Performance Characteristics (Continued)
Bode Plot Slew Rate
00564928 00564929
Distortion vs. Frequency Undistorted Output Voltage Swing
0056493000564931
Open Loop Frequency Response Common-Mode Rejection Ratio
00564932 00564933
LF353
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Typical Performance Characteristics (Continued)
Power Supply Rejection Ratio Equivalent Input Noise Voltage
0056493400564935
Open Loop Voltage Gain (V/V) Output Impedance
00564936 00564937
Inverter Settling Time
00564938
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Pulse ResponseSmall Signaling Inverting
00564904
Large Signal Inverting
00564906
Small Signal Non-Inverting
00564905
Large Signal Non-Inverting
00564907
Current Limit (RL = 100Ω)
00564908
Application HintsThese devices are op amps with an internally trimmed inputoffset voltage and JFET input devices (BI-FET II). TheseJFETs have large reverse breakdown voltages from gate tosource and drain eliminating the need for clamps across theinputs. Therefore, large differential input voltages can easilybe accommodated without a large increase in input current.The maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltagesshould be allowed to exceed the negative supply as this willcause large currents to flow which can result in a destroyedunit.
Exceeding the negative common-mode limit on either inputwill force the output to a high state, potentially causing areversal of phase to the output. Exceeding the negativecommon-mode limit on both inputs will force the amplifieroutput to a high state. In neither case does a latch occur
LF353
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Application Hints (Continued)
since raising the input back within the common-mode rangeagain puts the input stage and thus the amplifier in a normaloperating mode.
Exceeding the positive common-mode limit on a single inputwill not change the phase of the output; however, if bothinputs exceed the limit, the output of the amplifier will beforced to a high state.
The amplifiers will operate with a common-mode input volt-age equal to the positive supply; however, the gain band-width and slew rate may be decreased in this condition.When the negative common-mode voltage swings to within3V of the negative supply, an increase in input offset voltagemay occur.
Each amplifier is individually biased by a zener referencewhich allows normal circuit operation on ±6V power sup-plies. Supply voltages less than these may result in lowergain bandwidth and slew rate.
The amplifiers will drive a 2 kΩ load resistance to ±10V overthe full temperature range of 0˚C to +70˚C. If the amplifier isforced to drive heavier load currents, however, an increasein input offset voltage may occur on the negative voltageswing and finally reach an active current limit on both posi-tive and negative swings.
Precautions should be taken to ensure that the power supplyfor the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in asocket as an unlimited current surge through the resultingforward diode within the IC could cause fusing of the internalconductors and result in a destroyed unit.
As with most amplifiers, care should be taken with leaddress, component placement and supply decoupling in orderto ensure stability. For example, resistors from the output toan input should be placed with the body close to the input tominimize “pick-up” and maximize the frequency of the feed-back pole by minimizing the capacitance from the input toground.
A feedback pole is created when the feedback around anyamplifier is resistive. The parallel resistance and capacitancefrom the input of the device (usually the inverting input) to ACground set the frequency of the pole. In many instances thefrequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently thereis negligible effect on stability margin. However, if the feed-back pole is less than approximately 6 times the expected 3dB frequency a lead capacitor should be placed from theoutput to the input of the op amp. The value of the addedcapacitor should be such that the RC time constant of thiscapacitor and the resistance it parallels is greater than orequal to the original feedback pole time constant.
Detailed Schematic
00564909
LF35
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Typical ApplicationsThree-Band Active Tone Control
Order Number LF353M or LF353MXNS Package Number M08A
Molded Dual-In-Line PackageOrder Number LF353N
NS Package N08E
LF353
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.
2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer ProductsStewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National SemiconductorAmericas CustomerSupport CenterEmail: [email protected]: 1-800-272-9959
National SemiconductorEurope Customer Support Center
National SemiconductorAsia Pacific CustomerSupport CenterEmail: [email protected]
National SemiconductorJapan Customer Support CenterFax: 81-3-5639-7507Email: [email protected]: 81-3-5639-7560
www.national.com
LF35
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
JFET Input Operational Amplifiers
These low cost JFET input operational amplifiers combine twostate–of–the–art analog technologies on a single monolithic integratedcircuit. Each internally compensated operational amplifier has well matchedhigh voltage JFET input devices for low input offset voltage. The JFETtechnology provides wide bandwidths and fast slew rates with low input biascurrents, input offset currents, and supply currents.
These devices are available in single, dual and quad operationalamplifiers which are pin–compatible with the industry standard MC1741,MC1458, and the MC3403/LM324 bipolar devices.
• Input Offset Voltage of 5.0 mV Max (LF347B)
• Low Input Bias Current: 50 pA
• Low Input Noise Voltage: 16 nV/ Hz
• Wide Gain Bandwidth: 4.0 MHz
• High Slew Rate: 13V/µs
• Low Supply Current: 1.8 mA per Amplifier
• High Input Impedance: 1012 Ω• High Common Mode and Supply Voltage Rejection Ratios: 100 dB
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC +18 VVEE –18
Differential Input Voltage VID ±30 V
Input Voltage Range (Note 1) VIDR ±15 V
Output Short Circuit Duration (Note 2) tSC Continuous
Power Dissipation at TA = +25°C PD 900 mWDerate above TA =+25°C 1/θJA 10 mW/°C
Operating Ambient Temperature Range TA 0 to +70 °C
Operating Junction Temperature Range TJ 115 °C
Storage Temperature Range Tstg – 65 to+150
°C
NOTES: 1. Unless otherwise specified, the absolute maximum negative input voltage islimited to the negative power supply.
2. Any amplifier output can be shorted to ground indefinitely. However, if more thanone amplifier output is shorted simultaneously, maximum junction temperaturerating may be exceeded.
ON Semiconductor
Semiconductor Components Industries, LLC, 2002
March, 2002 – Rev. 11 Publication Order Number:
LF347/D
LF347, BLF351LF353
FAMILY OF JFETOPERATIONAL AMPLIFIERS
D SUFFIXPLASTIC PACKAGE
CASE 751(SO–8)
N SUFFIXPLASTIC PACKAGE
CASE 626
1
1
8
8
Output A
Inputs A
VEE
VCC
Output B
Inputs B
LF351(Top View)
LF353(Top View)
Offset Null
Invt Input
Noninvt Input
VEE
NC
VCC
Output
Offset Null
1
2
3
4
8
7
6
5
+
-
-
-+
+
A
B
1
2
3
4
8
7
6
5
PIN CONNECTIONS
N SUFFIXPLASTIC PACKAGE
CASE 64614
1
(Top View)
Out 1
Inputs 1
VCC
Inputs 2
Out 2
Out 4
Inputs 4
VEE
Inputs 3
Out 3
1
2
3
4
5
6
7 8
9
10
11
12
13
14
4
2 3
+ +
+ +
1
- -
- -
PIN CONNECTIONS
ORDERING INFORMATION
FunctionDevice PackageOperating
Temperature Range
LF351DLF351N
SingleSingle
TA = 0° to +70°C
SO–8Plastic DIP
LF353DLF353N
DualDual
SO–8Plastic DIP
LF347BNLF347N
QuadQuad
Plastic DIPPlastic DIP
LF347, B LF351 LF353
http://onsemi.com2
ELECTRICAL CHARACTERISTICS (VCC = +15 VEE = –15 V, TA = 25°C, unless otherwise noted.)
LF347B LF347, LF351, LF353
Characteristic Symbol Min Typ Max Min Typ Max Unit
For Typical Characteristic Performance Curves, refer to MC34001, 34002, 34004 data sheet.
NOTE: 3. Input bias currents of JFET input op amps approximately double for every 10°C rise in junction temperature. To maintain junction temperatures as close to ambient as is possible, pulse techniques are utilized during test.
LF347, B LF351 LF353
http://onsemi.com3
OUTLINE DIMENSIONS
NOTES:1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
58
F
NOTE 2 –A–
–B–
–T–SEATING
PLANE
H
J
G
D K
N
C
L
M
MAM0.13 (0.005) B MT
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M --- 10 --- 10
N 0.76 1.01 0.030 0.040
D SUFFIXPLASTIC PACKAGE
CASE 751–05(SO–8)
ISSUE R
N SUFFIXPLASTIC PACKAGE
CASE 626–05ISSUE K
SEATING
PLANE
1
4
58
A0.25 M C B S S
0.25 M B M
h
C
X 45
L
DIM MIN MAX
MILLIMETERS
A 1.35 1.75
A1 0.10 0.25
B 0.35 0.49
C 0.18 0.25
D 4.80 5.00
E
1.27 BSCe
3.80 4.00
H 5.80 6.20
h
0 7 L 0.40 1.25
0.25 0.50
NOTES:1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.2. DIMENSIONS ARE IN MILLIMETERS.3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 TOTAL IN EXCESSOF THE B DIMENSION AT MAXIMUM MATERIALCONDITION.
D
E H
A
B e
BA1
C A
0.10
LF347, B LF351 LF353
http://onsemi.com4
OUTLINE DIMENSIONS
NOTES:1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUMMATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLDFLASH.
4. ROUNDED CORNERS OPTIONAL.1 7
14 8
B
A
F
H G DK
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01
N SUFFIXPLASTIC PACKAGE
CASE 646–06ISSUE L
ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the rightto make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its productsfor any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims anyand all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheetsand/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” mustbe validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or deathmay occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLCand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatSCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATIONJAPAN : ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031Phone : 81–3–5740–2700Email : [email protected]
ON Semiconductor Website : http://onsemi.com
For additional information, please contact your localSales Representative.
LF347/D
Literature Fulfillment :Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone : 303–675–2175 or 800–344–3860 Toll Free USA/CanadaFax: 303–675–2176 or 800–344–3867 Toll Free USA/CanadaEmail : [email protected]
N. American Technical Support : 800–282–9855 Toll Free USA/Canada
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Supply Voltage (VDD) b0.5 to a18 VDC
Input Voltage (VIN) b0.5 to VDD a0.5 VDC
Storage Temperature Range (TS) b65§C to a150§CPower Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260§C
Recommended OperatingConditions (Note 2)
DC Supply Voltage (VDD) 3 to 15 VDC
Input Voltage (VIN) 0 to VDD VDC
Operating Temperature Range (TA)
CD4093BM b55§C to a125§CCD4093BC b40§C to a85§C
DC Electrical Characteristics CD4093BM (Note 2)
Symbol Parameter Conditionsb55§C a25§C a125§C
UnitsMin Max Min Typ Max Min Max
IDD Quiescent Device VDD e 5V 0.25 0.25 7.5 mA
Current VDD e 10V 0.5 0.5 15.0 mA
VDD e 15V 1.0 1.0 30.0 mA
VOL Low Level VIN e VDD, lIOl k 1 mA
Output Voltage VDD e 5V 0.05 0 0.05 0.05 V
VDD e 10V 0.05 0 0.05 0.05 V
VDD e 15V 0.05 0 0.05 0.05 V
VOH High Level VIN e VSS, lIOl k 1 mA
Output Voltage VDD e 5V 4.95 4.95 5 4.95 V
VDD e 10V 9.95 9.95 10 9.95 V
VDD e 15V 14.95 14.95 15 14.95 V
VTb Negative-Going Threshold lIOl k 1 mA
Voltage (Any Input) VDD e 5V, VO e 4.5V 1.3 2.25 1.5 1.8 2.25 1.5 2.3 V
VDD e 10V, VO e 9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65 V
VDD e 15V, VO e 13.5V 4.35 6.75 4.5 6.3 6.75 4.5 6.9 V
VTa Positive-Going Threshold lIOl k 1 mA
Voltage (Any Input) VDD e 5V, VO e 0.5V 2.75 3.65 2.75 3.3 3.5 2.65 3.5 V
VDD e 10V, VO e 1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0 V
VDD e 15V, VO e 1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5 V
VH Hysteresis (VTa b VT
b) VDD e 5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V
(Any Input) VDD e 10V 1.0 4.30 1.0 2.2 4.0 0.70 4.0 V
VDD e 15V 1.5 6.30 1.5 2.7 6.0 1.20 6.0 V
IOL Low Level Output VIN e VDD
Current (Note 3) VDD e 5V, VO e 0.4V 0.64 0.51 0.88 0.36 mA
VDD e 10V, VO e 0.5V 1.6 1.3 2.25 0.9 mA
VDD e 15V, VO e 1.5V 4.2 3.4 8.8 2.4 mA
IOH High Level Output VIN e VSS
Current (Note 3) VDD e 5V, VO e 4.6V b0.64 0.51 b0.88 b0.36 mA
VDD e 10V, VO e 9.5V b1.6 b1.3 b2.25 b0.9 mA
VDD e 15V, VO e 13.5V b4.2 b3.4 b8.8 b2.4 mA
IIN Input Current VDD e 15V, VIN e 0V b0.1 b10b5 b0.1 b1.0 mA
VDD e 15V, VIN e 15V 0.1 10b5 0.1 1.0 mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
2
DC Electrical Characteristics CD4093BC (Note 2)
Symbol Parameter Conditionsb40§C a25§C a85§C
UnitsMin Max Min Typ Max Min Max
IDD Quiescent Device VDD e 5V 1.0 1.0 7.5 mA
Current VDD e 10V 2.0 2.0 15.0 mA
VDD e 15V 4.0 4.0 30.0 mA
VOL Low Level VIN e VDD, lIOl k 1 mA
Output Voltage VDD e 5V 0.05 0 0.05 0.05 V
VDD e 10V 0.05 0 0.05 0.05 V
VDD e 15V 0.05 0 0.05 0.05 V
VOH High Level VIN e VSS, lIOl k 1 mA
Output Voltage VDD e 5V 4.95 4.95 5 4.95 V
VDD e 10V 9.95 9.95 10 9.95 V
VDD e 15V 14.95 14.95 15 14.95 V
VTb Negative-Going Threshold lIOl k 1 mA
Voltage (Any Input) VDD e 5V, VO e 4.5V 1.3 2.25 1.5 1.8 2.25 1.5 2.3 V
VDD e 10V, VO e 9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65 V
VDD e 15V, VO e 13.5V 4.35 6.75 4.5 6.3 6.75 4.5 6.9 V
VTa Positive-Going Threshold lIOl k 1 mA
Voltage (Any Input) VDD e 5V, VO e 0.5V 2.75 3.6 2.75 3.3 3.5 2.65 3.5 V
VDD e 10V, VO e 1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0 V
VDD e 15V, VO e 1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5 V
VH Hysteresis (VTa b VT
b) VDD e 5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V
(Any Input) VDD e 10V 1.0 4.3 1.0 2.2 4.0 0.70 4.0 V
VDD e 15V 1.5 6.3 1.5 2.7 6.0 1.20 6.0 V
IOL Low Level Output VIN e VDD
Current (Note 3) VDD e 5V, VO e 0.4V 0.52 0.44 0.88 0.36 mA
VDD e 10V, VO e 0.5V 1.3 1.1 2.25 0.9 mA
VDD e 15V, VO e 1.5V 3.6 3.0 8.8 2.4 mA
IOH High Level Output VIN e VSS
Current (Note 3) VDD e 5V, VO e 4.6V b0.52 0.44 b0.88 b0.36 mA
VDD e 10V, VO e 9.5V b1.3 b1.1 b2.25 b0.9 mA
VDD e 15V, VO e 13.5V b3.6 b3.0 b8.8 b2.4 mA
IIN Input Current VDD e 15V, VIN e 0V b0.3 b10b5 b0.3 b1.0 mA
VDD e 15V, VIN e 15V 0.3 10b5 0.3 1.0 mA
AC Electrical Characteristics*TA e 25§C, CL e 50 pF, RL e 200k, Input tr, tf e 20 ns, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
tPHL, tPLH Propagation Delay Time VDD e 5V 300 450 ns
VDD e 10V 120 210 ns
VDD e 15V 80 160 ns
tTHL, tTLH Transition Time VDD e 5V 90 145 ns
VDD e 10V 50 75 ns
VDD e 15V 40 60 ns
CIN Input Capacitance (Any Input) 5.0 7.5 pF
CPD Power Dissipation Capacitance (Per Gate) 24 pF
*AC Parameters are guaranteed by DC correlated testing.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
3
Typical ApplicationsGated Oscillator
TL/F/5982–2
Assume t1 a t2 ll tPHL a tPLH then:
t0 e RC fin [VDD/VTb]
t1 e RC fin [(VDD b VTb)/(VDD b VT
a)]
t2 e RC fin [VTa/V
Tb]
f e
1
t1 a t2e
1
RC fin(VT
a) (VDD b VTb)
(VTb)(VDD b VT
a)
TL/F/5982–3
Gated One-Shot
TL/F/5982–4
TL/F/5982–5
(a) Negative-Edge Triggered
TL/F/5982–6
TL/F/5982–7
(b) Positive-Edge Triggered
4
Typical Performance Characteristics
Typical Transfer
Characteristics
TL/F/5982–8
Guaranteed Hysteresis vs VDD
TL/F/5982–9
Guaranteed Trigger Threshold
Voltage vs VDD
TL/F/5982–10
Guaranteed Hysteresis vs VDD
TL/F/5982–11
Input and Output Characteristics
TL/F/5982–12
Output Characteristic Input Characteristic
TL/F/5982–13
VNML e VIH(MIN) b VOL j VIH(MIN) e VTa
(MIN)
VNMH e VOH b VIL(MAX) j VDD b VIL(MAX) e VDD b VTb
(MAX)
AC Test Circuits and Switching Time Waveforms
TL/F/5982–14
TL/F/5982–15
5
CD
4093B
M/C
D4093B
CQ
uad
2-InputN
AN
DSchm
ittTrigger
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4093BMJ or CD4093BCJ
NS Package Number J14A
Molded Dual-In-Line Package (N)
Order Number CD4093BM or CD4093BCN
NS Package Number N14A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Semiconductor Components Industries, LLC, 2000
August, 2000 – Rev. 41 Publication Order Number:
MC14013B/D
MC14013B
Dual Type D Flip-FlopThe MC14013B dual type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each flip–flop has independent Data, (D), DirectSet, (S), Direct Reset, (R), and Clock (C) inputs and complementaryoutputs (Q and Q). These devices may be used as shift registerelements or as type T flip–flops for counter and toggle applications.
• Static Operation
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop DesignLogic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive–goingedge of the clock pulse
• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4013B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range –0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range(DC or Transient)
–0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current(DC or Transient) per Pin
±10 mA
PD Power Dissipation,per Package (Note 3.)
500 mW
TA Ambient Temperature Range –55 to +125 °C
Tstg Storage Temperature Range –65 to +150 °C
TL Lead Temperature(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the devicemay occur.
3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, Vin and Vout should be constrainedto the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
A = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14013BCP PDIP–14 2000/Box
MC14013BD SOIC–14 55/Rail
MC14013BDR2 SOIC–14 2500/Tape & Reel
MC14013BDT TSSOP–14
MC14013BF SOEIAJ–14
96/Rail
See Note 1.
MARKINGDIAGRAMS
1
14PDIP–14P SUFFIXCASE 646
MC14013BCPAWLYYWW
SOIC–14D SUFFIX
CASE 751A
TSSOP–14DT SUFFIXCASE 948G
1
14
14013BAWLYWW
14013BALYW
1
14
SOEIAJ–14F SUFFIXCASE 965
1
14
MC14013BALYW
MC14013BFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.
IT = (0.75 µA/kHz) f + IDDIT = (1.5 µA/kHz) f + IDDIT = (2.3 µA/kHz) f + IDD
ÎÎÎÎÎÎÎÎÎÎÎÎ
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25C.6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
ÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)
R
C
D
SC
C
C C
C
C
C
CC
C
Q
Q
MC14013B
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Figure 1. Dynamic Signal Waveforms(Data, Clock, and Output)
Figure 2. Dynamic Signal Waveforms(Set, Reset, Clock, and Output)
20 ns 20 ns
D
C
Q
90%50%
10%tsu (H) tsu (L)
th
tWH tWL
90%50%
10%
VDD
VSS
VDD
VSS
VOH
VOL
tTLH tTHL
tPHLtPLH
90%50%10%
Inputs R and S low.
1
fcl
20 ns 20 ns
SET OR
RESET
CLOCK
Q OR Q
90%50%
10%
VDD
VSS
VDD
VSS
VOH
VOL
20 ns 20 nstrem
90%50%
10%
50%
tPLH
tPHL
tw
20 ns
tw
TYPICAL APPLICATIONS
n–STAGE SHIFT REGISTER
BINARY RIPPLE UP–COUNTER (Divide–by–2n)
MODIFIED RING COUNTER (Divide–by–(n+1))
D
CLOCK
nth21
QD
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK
nth21
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
Q
T FLIP-FLOP
nth21
QD
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK
MC14013B
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PACKAGE DIMENSIONS
P SUFFIXPLASTIC DIP PACKAGE
CASE 646–06ISSUE M
1 7
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
M --- 10 --- 10
N 0.015 0.039 0.38 1.01
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.
F
H G DK
C
SEATING
PLANE
N
–T–
14 PL
M0.13 (0.005)
L
MJ
0.290 0.310 7.37 7.87
D SUFFIXPLASTIC SOIC PACKAGE
CASE 751A–03ISSUE F
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P 7 PL
14 8
71M0.25 (0.010) B M
SBM0.25 (0.010) A ST
–T–
FR X 45
SEATING
PLANED 14 PL K
C
JM
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
MC14013B
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PACKAGE DIMENSIONS
DT SUFFIXPLASTIC TSSOP PACKAGE
CASE 948G–01ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLDFLASH OR GATE BURRS SHALL NOT EXCEED0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL NOTEXCEED0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7. DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE -W-.
SU0.15 (0.006) T
2X L/2
SUM0.10 (0.004) V ST
L–U–
SEATING
PLANE
0.10 (0.004)
–T–
ÇÇÇÇÇÇSECTION N–N
DETAIL E
J J1
K
K1
ÉÉÉÉ
DETAIL E
F
M
–W–
0.25 (0.010)814
71
PIN 1IDENT.
HG
A
D
C
B
SU0.15 (0.006) T
–V–
14X REFK
N
N
F SUFFIXPLASTIC EIAJ SOIC PACKAGE
CASE 965–01ISSUE O
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
10 0 10
LE
Q1
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).
0.13 (0.005) M 0.10 (0.004)
DZ
E
1
14 8
7
e A
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
MC14013B
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