FILTER PELEWAT RENDAH TERKENDALI DIGITAL TUGAS AKHIR Diajukan untuk memenuhi salah satu syarat Memperoleh gelar Sarjana Teknik Program Studi Teknik Elektro i Disusun oleh: HADI SANJAYA NIM : 005114061 PROGRAM STUDI TEKNIK ELEKTRO JURUSAN TEKNIK ELEKTRO FAKULTAS SAINS DAN TEKNOLOGI UNIVERSITAS SANATA DHARMA YOGYAKARTA 2007
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FILTER PELEWAT RENDAH TERKENDALI DIGITAL · untuk rangkaian integrator pada rangkaian tapis peubah kondisi. Nilai masukan digital Nilai masukan digital ditampilkan oleh LED dan frekuensi
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FILTER PELEWAT RENDAH TERKENDALI DIGITAL
TUGAS AKHIR
Diajukan untuk memenuhi salah satu syarat Memperoleh gelar Sarjana Teknik
Program Studi Teknik Elektro
i
Disusun oleh:
HADI SANJAYA
NIM : 005114061
PROGRAM STUDI TEKNIK ELEKTRO JURUSAN TEKNIK ELEKTRO
FAKULTAS SAINS DAN TEKNOLOGI UNIVERSITAS SANATA DHARMA
YOGYAKARTA 2007
DIGITALLY CONTROLLED LOW PASS FILTER
FINAL PROJECT
Presented as Partial Fulfillment of the Requirements
To Obtain the Sarjana Teknik Degree
In Electrical Engineering
ii
By : HADI SANJAYA
Student ID Number : 005114061
ELECTRICAL ENGINEERING STUDY PROGRAM ELECTRICAL ENGINEERING DEPARTMENT
SAINS AND TECHNOLOGY FACULTY SANATA DHARMA UNIVERSITY
YOGYAKARTA 2007
iii
iv
v
Katakanlah: “Dialah Allah adalah Yang Maha Esa”. Hanya Allah tempat bergantung. Dia tidak beranak dan tidak diperanakkan. Dan tidak ada satupun yang menyamai-Nya”.
(Al Ikhlash)
Karya ini kupersembahankan untuk :
Allah SWT dan junjungan Nabi Muhammad SAW (atas berkat dan rahmat-Nya)
Bapak Iswandi Umar & Ibu Sumarni yang selalu memberikan doa, kekuatan dan mendidikku
dengan penuh cinta, Kakakku Eko Susanto & Adik-
adikku Mira Tulistiana, Nery Indriana, terima kasih
atas dukungannya, Almamaterku
vi
vii
INTISARI
Filter pelewat rendah terkendali digital adalah filter pelewat rendah, dengan frekuensi penggal yang dapat dikendalikan secara digital dengan menggunakan masukan kode digital. Secara umum alat ini terdiri dari bagian digital dan bagian analog. Bagian digital terdiri dari pengendali masukan digital dan pengali, dan bagian analog terdiri dari filter pelewat rendah. Untuk pengendali masukan digital menggunakan 8 saklar dan untuk pengali menggunakan DAC 0832. Jadi frekuensi penggal pada filter ditala secara digital tergantung dari besarnya nilai dari masukan digital. Untuk filter digunakan filter jenis tapis peubah kondisi dengan tujuan agar saat frekuensi penggal diubah-ubah, faktor kualitasnya tetap. Proses perkalian antara masukan digital dengan komponen pengali ‘k’ dan tegangan referensi keluaran dari penguat beda pada rangkaian tapis peubah kondisi. Hasil perkalian merupakan masukan untuk rangkaian integrator pada rangkaian tapis peubah kondisi. Nilai masukan digital ditampilkan oleh LED dan frekuensi penggal diukur dengan menggunakan osiloskop. Pada tanggapan magnitude diperoleh laju kemiringan (roll-off) yang mempunyai kesalahan rata-rata sebesar 4,1 % dibandingkan dengan nilai teoritis, dan untuk pengukuraan frekuensi penggal didapatkan kesalahan rata-rata sebesar 2,36 % dibaningkan nilai teoritis.
kata kunci : filter pelewat rendah, masukan digital
viii
ABSTRACT
Digitally controlled low pass filter is low pass filter that cut-off frequency of filter could be controlled digitally using binary code digital. This appliance consist of digital part and analog part. Part of digital consist of digital input controller and multiplier. Part of analog consist of low pass filter. Digital input use eight switch and multiplier component use DAC 0832. The cut-off frequency was tuned digitally depend of digital input value. The filter use State Variable Filter (SVF) type which so that quality factor (Q) of filter kept constant. Multiplying operation between digital input voltage with multiplier component called as ‘k’, and reference voltage from differensiator on state variable filter. The output of multiplier use as input to integrator on state variable filter. The value of digital input was displayed by LED and the cut-off frequency was measure by osciloscope. From the magnitude response can be analyzed the roll-off value and it has an error about 4,1 % and for measurement of cut-off frequency has an error about 2,36 % from theory value. keyword : low pass filter, digital input
ix
KATA PENGANTAR
Dengan menyebut nama Allah yang Maha Pengasih lagi Maha Penyayang, oleh
karena petunjuk dan rahmat-Nya sehingga penulis dapat meyelesaikan Tugas Akhir
yang berjudul “Filter Pelewat Rendah Terkendali Digital”. Tugas Akhir ini disusun
sebagai salah satu syarat untuk memperoleh gelar Sarjana pada jurusan Teknik Elektro,
Fakultas Teknik Universitas Sanatha Dharma Yogyakarta.
Tersusunnya tugas akhir ini tidak terlepas dari bantuan dan dukungan dari berbagai
pihak. Pada kesempatan ini tidak lupa penulis mengucapkan terima kasih yang dalam
kepada :
1. Bapak Martanto, S.T., M.T., selaku Dosen Pembimbing I yang telah banyak
memberikan bimbingan dan pengarahan hingga tugas akhir ini dapat tersusun.
2. Bapak Ir. Tjendro, selaku dosen pembimbing II atas bimbingan dan bantuannya
sehingga penulis dapat menyelesaikan tugas akhir ini.
3. Bapak Djoko Untoro, S.Si., M.T., selaku Dosen Penguji yang telah memberikan
masukan dan saran.
4. Ibu Ir. Th. Prima Ari Setyani, M.T., selaku Dosen Penguji yang telah memberikan
masukan dan saran.
5. Bapak Iswandi Umar dan Ibunda Sumarni yang telah memberikan kasih dan
sayangnya, doa, dorongan, semangat, biaya yang tiada henti hingga terselesaikan
studi dan penyusunan tugas akhir ini.
6. Kakakku Eko Susanto dan Adik-adikku Mira Tulistiana, Nery Indriana atas
dukungan dan semangatnya.
x
xi
DAFTAR ISI
HALAMAN JUDUL ......................................................................................... .. i
HALAMAN PERSETUJUAN PEMBIMBING .............................................. .. iii
HALAMAN PENGESAHAN ........................................................................... .. iv
HALAMAN PERNYATAAN KEASLIAN KARYA ..................................... .. v
HALAMAN PERSEMBAHAN ........................................................................ .. vi
INTISARI ................. ......................................................................................... .. vii
ABSTRACT............... ......................................................................................... .. viii
KATA PENGANTAR ....................................................................................... .. ix
DAFTAR ISI ............ ......................................................................................... .. xi
DAFTAR TABEL .... ......................................................................................... .. xiv
DAFTAR GAMBAR ......................................................................................... .. xiv
DAFTAR LAMPIRAN ..................................................................................... .. xvi
BAB I PENDAHULUAN ......................................................................... .. 1
Berdasarkan tabel 4.7, dapat dibuat grafik tanggapan magnitude untuk
urutan rendah untuk hasil secara teoritis. Gambar 4.6 menunjukkan tanggapan
magnitude secara teoritis dari urutan ke 253 sampai urutan ke 255.
-14
-12
-10
-8
-6
-4
-2
0
2
100 1000 10000 100000
Frekuensi (Hz)
Peng
uata
n A
mpl
itud
o (d
B)
fc = 25500 Hz fc = 25400 Hz fc = 25300 Hz
Gambar 4.6 Tanggapan magnitude secara teoritis dari urutan ke 253 sampai urutan ke 255
Berdasarkan gambar 4.6, secara teoritis untuk urutan ke 253 frekuensi cut-off
adalah sebesar 25300 Hz, sebesar 25400 Hz saat urutan ke 254 dan sebesar 25500
saat urutan ke 255. Berdasarkan data hasil pengamatan pada tabel 4.4 dan data
secara teoritis pada tabel 4.5, dapat diketahui bahwa ada perbedaan nilai frekuensi
56
cut-off pengamatan dan nilai secara teoritis. Adapun besarnya kesalahannya
adalah sebagai berikut :
1) untuk urutan ke 253 (fc = 25,3 KHz)
%01,0%100Hz 25300
Hz 25300 -Hz 25305 =×
2) untuk urutan ke 254 (fc = 25,4 KHz)
%07,0%100Hz 25400
Hz 25400 -Hz 25420 =×
3) untuk urutan ke 255 (fc = 25,5 KHz)
%03,0%100Hz 25500
Hz 25500 -Hz 25510 =×
Berdasarkan grafik-grafik diatas, terlihat bahwa semakin besar nilai bit
yang dimasukkan ke pengali maka tanggapan magnitude semakin bergeser ke
kanan atau bergeser ke arah frekuensi yang lebih tinggi begitu pula dengan
penguatan amplitudo saat frekuensi cut-off.
4.2. Penaksiran Nilai Roll-off pada Tanggapan Magnitude Sebagai
Fungsi Frekuensi
Sub bab ini bertujuan untuk menunjukan nilai roll off pada urutan rendah
(urutan ke 1 (fc = 100Hz), urutan ke 2 (fc = 200Hz) dan urutan ke 3 (fc = 300
Hz)), urutan sedang (urutan ke 100 (fc = 10 KHz), urutan ke 101 (fc = 10,1 KHz)
dan urutan ke 102 (fc = 10,2 KHz)) dan urutan tinggi (urutan ke 253 (fc = 25,3
KHz), urutan ke 254 (fc = 25,4 KHz) dan urutan ke 255 (fc = 25,5 KHz)).
Berdasarkan grafik tanggapan magnitude pengamatan untuk urutan rendah, urutan
57
sedang dan urutan tinggi pada bahasan sub bab 4.1, dapat diamati nilai roll-off
pada tanggapan magnitude. Nilai roll-off ditentukan dari gradien antara penguatan
amplitudo decibel terhadap jangkauan frekuensi tertentu. Secara teoritis, nilai roll-
off untuk penaksiran Butterworth dapat dinyatakan sebagai berikut :
Roll-off = oktaf/dB6.n -
Dengan n adalah jumlah kutub. Untuk jangkauan frekuensi 1 oktaf adalah sebesar
2 × frekuensi cut-off. Jadi secara teoritis, nilai roll-off untuk tanggapan
magnitude Butterworth 2 kutub adalah sebesar -12 dB/oktaf.
Untuk mengetahui nilai roll-off pada tanggapan magnitude dari
pengamatan urutan rendah, dari grafik tanggapan magnitude untuk bit rendah
dibuat gradien nilai roll-off dengan x∆ adalah jangkauan frekuensi satu oktaf dan
y∆ adalah jangkauan penguatan amplitudo decibel serta dengan kemiringan
merupakan garis yang menghubungkan titik 0 dB yang sejajar vertikal dengan
frekuensi cut-off pada -3 dB dengan titik dimana didapatkan penguatan decibel
saat frekuensi mencapai 2 × frekuensi cut-off (1 oktaf) . Hal yang sama juga
dilakukan untuk urutan sedang dan urutan tinggi.
Penaksiran nilai roll-off untuk urutan rendah dapat ditunjukkan oleh
gambar 4.7, 4.8 dan 4.9.
58
-21
-18
-15
-12
-9
-6
-3
0
10 100 1000
Frekuensi (Hz)
Peng
uata
n A
mpl
itud
o (d
B)
fc = 100 Hz
Gambar 4.7 Nilai roll-off tanggapan magnitude untuk urutan ke 1
-24
-21
-18
-15
-12
-9
-6
-3
0
3
10 100 1000
Frekuensi (Hz)
Peng
uata
n A
mpl
itud
o (d
B)
fc = 200 Hz
Gambar 4.8 Nilai roll-off tanggapan magnitude untuk urutan ke 2
59
-18
-15
-12
-9
-6
-3
0
3
10 100 1000
Frekuensi (Hz)
Peng
uata
n A
mpl
itud
o (d
B)
fc = 300 Hz
Gambar 4.9 Nilai roll-off tanggapan magnitude untuk urutan ke 3
Dari grafik penaksiran nilai roll-off pada gambar 4.7, 4.8 dan 4.9 dapat diketahui
nilai roll-off untuk urutan ke 1 (fc=100 Hz) adalah sebesar -12 dB/oktaf, untuk
urutan ke 2 (fc=200 Hz) sebesar -12 dB/oktaf dan untuk urutan ke 3 (fc = 300 Hz)
sebesar -12,995 dB/oktaf. Penaksiran nilai roll-off untuk urutan sedang dapat
ditunjukkan oleh gambar 4.10, 4.11 dan 4.12.
-21
-18
-15
-12
-9
-6
-3
0
3
100 1000 10000 100000
Frekuensi (Hz)
Pen
guat
an A
mpl
itud
o (d
B)
fc = 10000 Hz
Gambar 4.10 Nilai roll-off tanggapan magnitude untuk urutan ke 100
60
-21
-18
-15
-12
-9
-6
-3
0
3
100 1000 10000 100000
Frekuensi (Hz)
Pen
guat
an A
mpl
itudo
(dB
)
fc = 10100 Hz
Gambar 4.11 Nilai roll-off tanggapan magnitude untuk urutan ke 101
-21
-18
-15
-12
-9
-6
-3
0
3
100 1000 10000 100000
Frekuensi (Hz)
Peng
uata
n Am
plitud
o (d
B)
fc = 10200 Hz
Gambar 4.12 Nilai roll-off tanggapan magnitude untuk urutan ke 102
Dari grafik penaksiran nilai roll-off pada gambar 4.10, 4.11 dan 4.12 dapat
diketahui nilai roll-off untuk urutan ke 100 (fc = 10 KHz) adalah sebesar -11,56
dB/oktaf, untuk urutan ke 101 (fc = 10,1 KHz) sebesar -11,56 dB/oktaf dan untuk
urutan ke 102 (fc = 10,2 KHz) sebesar -11,3 dB/oktaf. Penaksiran nilai roll-off
untuk urutan tinggi dapat ditunjukkan oleh gambar 4.13, 4.14 dan 4.15.
61
-15
-12
-9
-6
-3
0
3
100 1000 10000 100000
Frekuensi (Hz)
Peng
uata
n A
mpl
itud
o (d
B)
urutan ke 253
Gambar 4.13 Nilai roll-off tanggapan magnitude untuk urutan ke 253
-15
-12
-9
-6
-3
0
3
100 1000 10000 100000
Frekuensi (Hz)
Peng
uata
n A
mpl
itud
o (d
B)
urutan ke 254
Gambar 4.14 Nilai roll-off tanggapan magnitude untuk urutan ke 254
62
-15
-12
-9
-6
-3
0
3
100 1000 10000 100000
Frekuensi (Hz)
Pen
guat
an A
mpl
itud
o (d
B)
urutan ke 255
Gambar 4.15 Nilai roll-off tanggapan magnitude untuk urutan ke 255
Dari grafik penaksiran nilai roll-off pada gambar 4.13, 4.14 dan 4.15 dapat
diketahui nilai roll-off untuk urutan ke 253 (fc = 25,3 KHz) adalah sebesar -11,43
dB/oktaf, untuk urutan ke 254 (fc =25,4 KHz) sebesar -11,83 dB/oktaf dan untuk
urutan ke 255 (fc = 35,5 KHz) sebesar -12,11 dB/oktaf.
Nilai roll-off pada tanggapan magnitude pengamatan untuk urutan
rendah, urutan sedang dan urutan tinggi dapat ditunjukkan oleh tabel 4.8.
Tabel 4.8. Penaksiran nilai roll-off pada tanggapan magnitude pengamatan
Urutan Roll-off (dB/oktaf)
Urutan ke 1 -12
Urutan ke 2 -12 Urutan Rendah
Urutan ke 3 -12,995
Urutan ke 100 -11,56
Urutan ke 101 -11,56 Urutan Sedang
Urutan ke 102 -11,3
Urutan ke 253 -11,437
Urutan ke 254 -11,835 Urutan Tinggi
Urutan ke 255 -12,11
63
Dari data penaksiran nilai roll-off pada tabel 4.8, nilai rata-rata untuk roll-off
tanggapan magnitude pengamatan untuk urutan rendah, urutan sedang dan urutan
tinggi adalah sebesar -11,86 dB/oktaf. Terjadi kesalahan sebesar 1,16 % dari
perhitungan secara teoritis.
4.3. Hubungan Antara Masukan Digital dengan Frekuensi cut-off
Sub bab ini bertujuan untuk mengetahui hubungan antara masukan
digital dengan frekuensi cut-off. Agar dapat dianalisis, maka dilakukan
pengamatan terhadap frekuensi cut-off (yang sekaligus diperoleh dari penguatan
amplitudo) setiap kenaikan 5 bit dari urutan rendah sampai urutan tinggi. Data
hasil pengamatan dan perhitungan secara teoritis adalah seperti ditunjukkan pada
lampiran A. Jika data-data tersebut dibuat dalam bentuk grafik, maka diperoleh
grafik yang menyatakan hubungan antara masukan digital dengan frekuensi cut-
off.
Untuk memperoleh frekuensi cut-off dari Low Pass Filter, sebagai
contoh mula-mula tegangan masukan, VI diatur sebesar 5 Vp-p , jika frekuensi
masukan diubah-ubah sedemikian rupa sehingga tegangan keluaran mencapai
amplitudo maksimum, maka untuk mencari frekuensi cut-off adalah mengatur
frekuensi masukan hingga mencapai amplitudo sebesar 0,707 dikalikan dengan
amplitudo maksimum.
Sebagai contoh, saat bit yang dimasukkan ke pengali bernilai 155(d), saat
frekuensi masukan diubah-ubah sehingga mencapai amplitudo maksimum dan
terukur amplitudo maksimum sebesar 5,04 Vp-p, sehingga nilai amplitudo pada
64
frekuensi cut-off sebesar 0,707 x 5,04 Vp-p adalah 3,563 Vp-p pada frekuensi 15430
Hz yang merupakan frekuensi cut-off. Hal yang sama juga dilakukan untuk
memperoleh frekuensi cut-off pada nilai bit yang lain.
Berdasarkan tabel 5 pada lampiran A, dapat dibuat grafik yang
menyatakan hubungan antara masukan digital dengan frekuensi cut-off. Gambar
4.16 menunjukkan grafik hubungan antara masukan digital dengan frekuensi cut-
off berdasarkan pengamatan dan teori.
0
5000
10000
15000
20000
25000
30000
0 50 100 150 200 250 300
Input (Desimal)
Fre
kuen
si P
usat
(H
z)
Frekuensi pusat (fo) Perancangan Frekuensi pusat (fo) Pengamatan
Gambar 4.16 Grafik hubungan antara masukan digital dengan frekuensi cut-off berdasarkan
pengamatan dan teori
Nilai rata-rata dari data pengamatan hubungan masukan digital dengan pergeseran
frekuensi cut-off untuk kenaikan 5 bit pada lampiran A adalah sebesar 501,71 Hz.
Terjadi kesalahan sebesar 0,342 % dari nilai perhitungan secara teoritis.
Hubungan suatu pengamatan sudah tentu memiliki nilai yang
menyimpang dari nilai secara teoritis. Nilai galat untuk menunjukkan
65
penyimpangan terhadap pengamatan dihitung untuk frekuensi cut-off.
Penyimpangan yang terjadi antara nilai hasil pengamatan dengan nilai secara
teoritis saat digital masukan tertentu dapat dihitung dengan persamaan galat,
yaitu:
%100 teorinilai
pengamatan nilai - teorinilai%Galat ×= (4.2)
Jika hasil pengamatan dan dan nilai secara teoritis dari frekuensi cut-off yang
terdapat pada lampiran A dimasukkan ke persamaan diatas, maka akan diperoleh
grafik hubungan antara masukan digital dengan galat. Berdasarkan tabel 5 pada
lampiran A, dapat dibuat grafik hubungan antara masukan digital dengan galat
untuk frekuensi cut-off. Gambar 4.17 menunjukkan grafik hubungan antara
masukan digital dengan galat untuk frekuensi cut-off.
-2
0
2
4
6
8
10
0 50 100 150 200 250 300
Input Digital
Gal
at %
Galat
Gambar 4.17 Grafik hubungan antara masukan digital dengan galat untuk frekuensi cut-off
66
Berdasarkan gambar 4.8, terlihat bahwa nilai galat tertinggi adalah sebesar 9,16 %
dan nilai galat terendah adalah sebesar 0,016 %. Nilai rata-rata galat untuk
frekuensi cut-off adalah sebesar 2,36 %.
4.4. Hubungan Antara Tegangan Referensi dengan Tegangan
Keluaran Pengali
Sub bab ini bertujuan untuk mengetahui apakah tegangan keluaran yang
dihasilkan merupakan perkalian antara masukan digital dengan tegangan referensi
pengali. Masukan digital diperoleh dari 8 saklar, saat saklar tidak terhubung
ground untuk masukan bit 1 (high) dan saat saklar terhubung ground untuk
masukan bit 0 (low), sedangkan tegangan referensi, Vref diperoleh secara langsung
dari keluaran penguat beda tingkat pertama saat AFG dihubungkan ke masukan
filter. Untuk tegangan keluaran pengali, jika dianalisis maka tegangan tersebut
merupakan perkalian antara tegangan referensi pengali dengan nilai bit yang
dimasukkan, yang sesuai dengan persamaan (2.29).
Sebagai contoh, jika di masukkan bit 125(d), terukur nilai tegangan
referensi sebesar 5,12 Vp-p, maka tegangan keluaran pengali diperoleh nilai
sebesar 2,6 Vp-p. Jika dibandingkan dengan dengan hasil secara teoritis, maka
tegangan keluaran pengali sebesar :
ppout VV −×= 12,5256
125
67
ppout VV −= 5,2
Berdasarkan tabel 7 pada lampiran B, dapat dibuat grafik hubungan
antara masukan digital dengan tegangan referensi dan tegangan keluaran pengali.
Gambar 4.18 menunjukkan grafik hubungan antara masukan digital dengan
tegangan referensi dan tegangan keluaran pengali.
0
0,2
0,4
0,6
0,8
1
1,2
0 50 100 150 200 250 300
Input Digital
Teg
anga
n R
efer
ensi/T
egan
gan
Out
put
Tegangan Referensi terhadap Tegangan Output (Pengamatan)
Tegangan Referensi terhadap Tegangan Output (Teori)
Gambar 4.18 Grafik hubungan antara masukan digital dengan tegangan referensi dan keluaran
pengali
Jika hasil pengamatan dan dan nilai secara teoritis dari tegangan keluaran pengali
yang terdapat pada lampiran B dimasukkan ke persamaan (4.2), maka akan
diperoleh grafik hubungan antara masukan digital dengan galat. Berdasarkan tabel
7 yang terdapat pada lampiran B, grafik hubungan antara masukan digital dengan
galat untuk tegangan keluaran pengali terhadap tegangan referensi yang
ditunjukkan oleh gambar 4.19
68
0
2
4
6
8
10
12
14
0 50 100 150 200 250 300
Input Digital
Gal
at %
Galat
Gambar 4.19 Grafik hubungan antara masukan digital dengan galat untuk tegangan keluaran
pengali
Berdasarkan gambar 4.19, nilai galat tertinggi adalah sebesar 12,820 % dan nilai
galat terendah adalah sebesar 0,358 %. Nilai rata-rata galat pada tegangan
keluaran terhadap tegangan referensi pengali adalah sebesar 3,20 %.
69
BAB V
KESIMPULAN DAN SARAN
1. Kesimpulan
Berdasarkan alat yang sudah dibuat dan dari data hasil pengamatan,
maka dapat disimpulkan sebagai berikut :
1. Alat ini dapat mengendalikan frekuensi cut-off untuk jangkauan frekuensi
cut off dari urutan rendah (urutan ke 1(fc=100 Hz)) sampai urutan tinggi
(urutan ke 255 (fc=255 Hz)) dari Filter Pelewat Rendah (Low Pass Filter)
dengan baik melalui input digital dari delapan saklar.
2. Semakin besar masukan digital maka pada tanggapan magnitude
perubahan frekuensi cut-off semakin ke arah frekuensi cut-off yang lebih
tinggi.
3. Pada percobaan untuk mengetahui hubungan masukan digital dan frekuensi
cut-off, untuk masukan digital dengan kenaikan setiap lima bit, pergeseran
frekuensi cut-off dari urutan rendah sampai urutan tinggi mengalami
kesalahan sebesar 0,342 % dari perhitungan secara teoritis. Nilai galat
tertinggi yaitu sebesar 9,16 % dan nilai galat terendah adalah sebesar 0,016
%.
4. Pada penaksiran nilai roll-off pada tanggapan magnitude pengamatan untuk
urutan rendah, urutan sedang dan urutan tinggi terjadi kesalahan sebesar
1,16 % dari perhitungan secara teoritis.
70
2. Saran
Alat ini masih dapat dikembangkan, untuk input digital, dapat memakai
counter dan untuk penampil dapat menggunakan tampilan seven segment dapat
berupa penampil bilangan desimal atau bilangan heksa. Untuk jenis filter dapat
dikembangkan dengan menggunakan jenis Filter Pelewat Jalur (Band Pass Filter),
Filter Pelewat Tinggi (High Pass Filter) dan Filter Penolak Jalur (Band Stop
Filter).
71
DAFTAR PUSTAKA
Boylestad, Robert, Nashelsky, Louis, 1996, Electronic Devices And Circuit Theory, Prentice-Hall, Inc., New Jersey. Putra, Afgianto Eko, 2002, Penapis Aktif Elektronika : Teori dan Praktek, C.V. Gava Media, Yogyakarta. Valkenburg, VME., 1982, Analog Filter Design, CBS College Publishing, New York. Irvine, Robert G., 1994, Operational Amplifier Characteristics And Applications, Prentice Hall, Inc., New Jersey.
LAMPIRAN
LAMPIRAN A
Tabel 5. Hubungan frekuensi cut-off dengan masukan digital
DAC0830/DAC08328-Bit µP Compatible, Double-Buffered D to A ConvertersGeneral DescriptionThe DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplyingDAC designed to interface directly with the 8080, 8048,8085, Z80®, and other popular microprocessors. A depositedsilicon-chromium R-2R resistor ladder network divides thereference current and provides the circuit with excellent tem-perature tracking characteristics (0.05% of Full Scale Rangemaximum linearity error over temperature). The circuit usesCMOS current switches and control logic to achieve lowpower consumption and low output leakage current errors.Special circuitry provides TTL logic input voltage level com-patibility.
Double buffering allows these DACs to output a voltage cor-responding to one digital word while holding the next digitalword. This permits the simultaneous updating of any numberof DACs.
The DAC0830 series are the 8-bit members of a family ofmicroprocessor-compatible DACs (MICRO-DAC™).
Featuresn Double-buffered, single-buffered or flow-through digital
data inputsn Easy interchange and pin-compatible with 12-bit
DAC1230 seriesn Direct interface to all popular microprocessorsn Linearity specified with zero and full scale adjust
only — NOT BEST STRAIGHT LINE FIT.n Works with ±10V reference-full 4-quadrant multiplicationn Can be used in the voltage switching moden Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)n Operates “STAND ALONE” (without µP) if desiredn Available in 20-pin small-outline or molded chip carrier
package
Key Specificationsn Current settling time: 1 µsn Resolution: 8 bitsn Linearity: 8, 9, or 10 bits (guaranteed over temp.)n Gain Tempco: 0.0002% FS/˚Cn Low power dissipation: 20 mWn Single power supply: 5 to 15 VDC
Typical Application
BI-FET™ and MICRO-DAC™ are trademarks of National Semiconductor Corporation.Z80® is a registered trademark of Zilog Corporation.
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) 17 VDC
Voltage at Any Digital Input VCC to GNDVoltage at VREF Input ±25VStorage Temperature Range −65˚C to +150˚CPackage Dissipation
at TA=25˚C (Note 3) 500 mWDC Voltage Applied to
IOUT1 or IOUT2 (Note 4) −100 mV to VCC
ESD Susceptability (Note 4) 800V
Lead Temperature (Soldering, 10 sec.)Dual-In-Line Package (plastic) 260˚CDual-In-Line Package (ceramic) 300˚CSurface Mount Package
Operating ConditionsTemperature Range TMIN≤TA≤TMAX
Part numbers with “LCN” suffix 0˚C to +70˚CPart numbers with “LCWM” suffix 0˚C to +70˚CPart numbers with “LCV” suffix 0˚C to +70˚CPart numbers with “LCJ” suffix −40˚C to +85˚CPart numbers with “LJ” suffix −55˚C to +125˚C
Voltage at Any Digital Input VCC to GND
Electrical CharacteristicsVREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, T MIN≤TA≤TMAX. For all other limitsTA=25˚C.
Parameter Conditions SeeNote
VCC = 4.75 VDCVCC = 15.75 VDC
VCC = 5 VDC ±5%VCC = 12 VDC ±5%
to 15 VDC ±5% LimitUnits
Typ(Note 12)
TestedLimit
(Note 5)
DesignLimit
(Note 6)
CONVERTER CHARACTERISTICS
Resolution 8 8 8 bits
Linearity Error Max Zero and full scale adjusted 4, 8
−10V≤VREF≤+10V
DAC0830LJ & LCJ 0.05 0.05 % FSR
DAC0832LJ & LCJ 0.2 0.2 % FSR
DAC0830LCN, LCWM &LCV
0.05 0.05 % FSR
DAC0831LCN 0.1 0.1 % FSR
DAC0832LCN, LCWM &LCV
0.2 0.2 % FSR
Differential Nonlinearity Zero and full scale adjusted 4, 8
Max −10V≤VREF≤+10V
DAC0830LJ & LCJ 0.1 0.1 % FSR
DAC0832LJ & LCJ 0.4 0.4 % FSR
DAC0830LCN, LCWM &LCV
0.1 0.1 % FSR
DAC0831LCN 0.2 0.2 % FSR
DAC0832LCN, LCWM &LCV
0.4 0.4 % FSR
Monotonicity −10V≤VREF LJ & LCJ 4 8 8 bits
≤+10V LCN, LCWM & LCV 8 8 bits
Gain Error Max Using Internal Rfb 7 ±0.2 ±1 ±1 % FS
−10V≤VREF≤+10V
Gain Error Tempco Max Using internal Rfb 0.0002 0.0006 %
FS/˚C
Power Supply Rejection All digital inputs latched high
tDS Data Setup Time VIL=0V, VIH=5V 9 100 250 375 600
Min 320 320 900 900
tDH Data Hold Time VIL=0V, VIH=5V 9 30 50 ns
Min 30 50
tCS Control Setup Time VIL=0V, VIH=5V 9 110 250 600 900
Min 320 320 1100 1100
tCH Control Hold Time VIL=0V, VIH=5V 9 0 0 10 0 0
Min 0 0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operatingthe device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
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Electrical Characteristics (Continued)
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximumallowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,TJMAX = 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N pack-age, this number increases to 100˚C/W and for the V package this number is 120˚C/W.
Note 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degradedby approximately VOS ÷ VREF. For example, if VREF = 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will introduce an additional 0.01% linearity error.
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at VREF=±10 VDC and VREF=±1 VDC.
Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-ticular VREF value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees thatafter performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xVREF of a straightline which passes through zero and full scale.
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
Note 10: A 100nA leakage current with Rfb=20k and VREF=10V corresponds to a zero error of (100x10−9x20x103)x100/10 which is 0.02% of FS.
Note 11: The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tS to apply.
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Switching Waveform
DS005608-2
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Definition of Package Pinouts
Control Signals (All control signals level actuated)
CS: Chip Select (active low). The CS in combinationwith ILE will enable WR1.
ILE: Input Latch Enable (active high). The ILE in combi-nation with CS enables WR1.
WR1: Write 1. The active low WR1 is used to load the digi-tal input data bits (DI) into the input latch. The datain the input latch is latched when WR1 is high. Toupdate the input latch–CS and WR1 must be lowwhile ILE is high.
WR2: Write 2 (active low). This signal, in combination withXFER, causes the 8-bit data which is available inthe input latch to transfer to the DAC register.
XFER: Transfer control signal (active low). The XFER willenable WR2.
Other Pin Functions
DI0-DI7: Digital Inputs. DI0 is the least significant bit (LSB)and DI7 is the most significant bit (MSB).
IOUT1: DAC Current Output 1. IOUT1 is a maximum for adigital code of all 1’s in the DAC register, and iszero for all 0’s in DAC register.
IOUT2: DAC Current Output 2. IOUT2 is a constant minusIOUT1 , or IOUT1 + IOUT2 = constant (I full scale fora fixed reference voltage).
Rfb: Feedback Resistor. The feedback resistor is pro-
vided on the IC chip for use as the shunt feedbackresistor for the external op amp which is used toprovide an output voltage for the DAC. This on-chip resistor should always be used (not an exter-nal resistor) since it matches the resistors whichare used in the on-chip R-2R ladder and tracksthese resistors over temperature.
VREF: Reference Voltage Input. This input connects anexternal precision voltage source to the internalR-2R ladder. VREF can be selected over the rangeof +10 to −10V. This is also the analog voltage in-put for a 4-quadrant multiplying DAC application.
VCC: Digital Supply Voltage . This is the power supplypin for the part. VCC can be from +5 to +15VDC.Operation is optimum for +15VDC
GND: The pin 10 voltage must be at the same groundpotential as IOUT1 and IOUT2 for current switchingapplications. Any difference of potential (VOS pin10) will result in a linearity change of
For example, if VREF = 10V and pin 10 is 9mV offset fromIOUT1 and IOUT2 the linearity change will be 0.03%.
Pin 3 can be offset ±100mV with no linearity change, but thelogic input threshold will shift.
Linearity Error
Definition of TermsResolution: Resolution is directly related to the number ofswitches or bits within the DAC. For example, the DAC0830has 28 or 256 steps and therefore has 8-bit resolution.
Linearity Error: Linearity Error is the maximum deviationfrom a straight line passing through the endpoints of theDAC transfer characteristic. It is measured after adjusting forzero and full-scale. Linearity error is a parameter intrinsic tothe device and cannot be externally adjusted.
National’s linearity “end point test” (a) and the “best straightline” test (b,c) used by other suppliers are illustrated above.The “end point test’’ greatly simplifies the adjustment proce-dure by eliminating the need for multiple iterations of check-ing the linearity and then adjusting full scale until the linearityis met. The “end point test’’ guarantees that linearity is metafter a single full scale adjust. (One adjustment vs. multiple
iterations of the adjustment.) The “end point test’’ uses astandard zero and F.S. adjustment procedure and is a muchmore stringent test for DAC linearity.
Power Supply Sensitivity: Power supply sensitivity is ameasure of the effect of power supply changes on the DACfull-scale output.
Settling Time: Settling time is the time required from a codetransition until the DAC output reaches within ±1⁄2LSB of thefinal output value. Full-scale settling time requires a zero tofull-scale or full-scale to zero output change.
Full Scale Error: Full scale error is a measure of the outputerror between an ideal DAC and the actual device output.Ideally, for the DAC0830 series, full scale is VREF −1LSB.For VREF = 10V and unipolar operation, VFULL-SCALE =10,0000V–39mV 9.961V. Full-scale error is adjustable tozero.
DS005608-23
a) End point test afterzero and fs adj.
DS005608-24
b) Best straight line DS005608-25
c) Shifting fs adj. to passbest straight line test
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Definition of Terms (Continued)
Differential Nonlinearity: The difference between any twoconsecutive codes in the transfer curve from the theoretical1 LSB to differential nonlinearity.
Monotonic: If the output of a DAC increases for increasingdigital input code, then the DAC is monotonic. An 8-bit DACwhich is monotonic to 8 bits simply means that increasingdigital input codes will produce an increasing analog output.
Typical Performance Characteristics
DS005608-4
FIGURE 1. DAC0830 Functional Diagram
Digital Input Thresholdvs. Temperature
DS005608-26
Digital Input Thresholdvs. VCC
DS005608-27
Gain and Linearity ErrorVariation vs. Temperature
DS005608-28
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Typical Performance Characteristics (Continued)
DAC0830 Series Application HintsThese DAC’s are the industry’s first microprocessor compat-ible, double-buffered 8-bit multiplying D to A converters.Double-buffering allows the utmost application flexibility froma digital control point of view. This 20-pin device is also pinfor pin compatible (with one exception) with the DAC1230, a12-bit MICRO-DAC. In the event that a system’s analog out-put resolution and accuracy must be upgraded, substitutingthe DAC1230 can be easily accomplished. By tying addressbit A0 to the ILE pin, a two-byte µP write instruction (doubleprecision) which automatically increments the address forthe second byte write (starting with A0=“1”) can be used.This allows either an 8-bit or the 12-bit part to be used withno hardware or software changes. For the simplest 8-bit ap-plication, this pin should be tied to VCC (also see other usesin section 1.1).
Analog signal control versatility is provided by a precisionR-2R ladder network which allows full 4-quadrant multiplica-tion of a wide range bipolar reference voltage by an applieddigital word.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC’s is that the 8-bitdigital input byte is double-buffered. This means that thedata must transfer through two independently controlled 8-bitlatching registers before being applied to the R-2R laddernetwork to change the analog output. The addition of a sec-ond register allows two useful control features. First, anyDAC in a system can simultaneously hold the current DACdata in one register (DAC register) and the next data word inthe second register (input register) to allow fast updating ofthe DAC output on demand. Second, and probably more im-portant, double-buffering allows any number of DAC’s in asystem to be updated to their new analog output levels si-multaneously via a common strobe signal.
The timing requirements and logic level convention of theregister control signals have been designed to minimize oreliminate external interfacing logic when applied to mostpopular microprocessors and development systems. It iseasy to think of these converters as 8-bit “write-only”memory locations that provide an analog output quantity. Allinputs to these DAC’s meet TTL voltage level specs and canalso be driven directly with high voltage CMOS logic innon-microprocessor based systems. To prevent damage tothe chip from static discharge, all unused digital inputsshould be tied to VCC or ground. If any of the digital inputsare inadvertantly left floating, the DAC interprets the pin as alogic “1”.
1.1 Double-Buffered Operation
Updating the analog output of these DAC’s in adouble-buffered manner is basically a two step or doublewrite operation. In a microprocessor system two unique sys-tem addresses must be decoded, one for the input latch con-trolled by the CS pin and a second for the DAC latch whichis controlled by the XFER line. If more than one DAC is beingdriven, Figure 2, the CS line of each DAC would typically bedecoded individually, but all of the converters could share acommon XFER address to allow simultaneous updating ofany number of DAC’s. The timing for this operation is shown,Figure 3.
It is important to note that the analog outputs that will changeafter a simultaneous transfer are those from the DAC’swhose input register had been modified prior to the XFERcommand.
Gain and Linearity ErrorVariation vs. Supply Voltage
DS005608-29
Write Pulse Width
DS005608-30
Data Hold Time
DS005608-31
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DAC0830 Series Application Hints (Continued)
The ILE pin is an active high chip select which can be de-coded from the address bus as a qualifier for the normal CSsignal generated during a write operation. This can be usedto provide a higher degree of decoding unique control sig-nals for a particular DAC, and thereby create a more efficientaddressing scheme.
Another useful application of the ILE pin of each DAC in amultiple DAC system is to tie these inputs together and usethis as a control line that can effectively “freeze” the outputsof all the DAC’s at their present value. Pulling this line lowlatches the input register and prevents new data from beingwritten to the DAC. This can be particularly useful in multi-processing systems to allow a processor other than the one
controlling the DAC’s to take over control of the data bus andcontrol lines. If this second system were to use the same ad-dresses as those decoded for DAC control (but for a differentpurpose) the ILE function would prevent the DAC’s from be-ing erroneously altered.
In a “Stand-Alone” system the control signals are generatedby discrete logic. In this case double-buffering can be con-trolled by simply taking CS and XFER to a logic “0”, ILE to alogic “1” and pulling WR1 low to load data to the input latch.Pulling WR2 low will then update the analog output. A logic“1” on either of these lines will prevent the changing of theanalog output.
DS005608-35
*TIE TO LOGIC 1 IF NOT NEEDED (SEE SEC. 1.1).
FIGURE 2. Controlling Mutiple DACs
DS005608-36
FIGURE 3.
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DAC0830 Series Application Hints (Continued)
1.2 Single-Buffered Operation
In a microprocessor controlled system where maximum datathroughput to the DAC is of primary concern, or when onlyone DAC of several needs to be updated at a time, asingle-buffered configuration can be used. One of the two in-ternal registers allows the data to flow through and the otherregister will serve as the data latch.
Digital signal feedthrough (see Section 1.5) is minimized ifthe input register is used as the data latch. Timing for thismode is shown in Figure 4.
Single-buffering in a “stand-alone” system is achieved bystrobing WR1 low to update the DAC with CS, WR2 andXFER grounded and ILE tied high.
1.3 Flow-Through Operation
Though primarily designed to provide microprocessor inter-face compatibility, the MICRO-DAC’s can easily be config-ured to allow the analog output to continuously reflect thestate of an applied digital input. This is most useful in appli-cations where the DAC is used in a continuous feedbackcontrol loop and is driven by a binary up-down counter, or infunction generation circuits where a ROM is continuouslyproviding DAC data.
Simply grounding CS, WR1, WR2, and XFER and tying ILEhigh allows both internal registers to follow the applied digitalinputs (flow-through) and directly affect the DAC analog out-put.
1.4 Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor,there are two important time relationships that must be con-sidered to insure proper operation. The first is the minimumWR strobe pulse width which is specified as 900 ns for allvalid operating conditions of supply voltage and ambienttemperature, but typically a pulse width of only 180ns is ad-equate if VCC=15VDC. A second consideration is that theguaranteed minimum data hold time of 50ns should be met
or erroneous data can be latched. This hold time is definedas the length of time data must be held valid on the digital in-puts after a qualified (via CS) WR strobe makes a low to hightransition to latch the applied data.
If the controlling device or system does not inherently meetthese timing specs the DAC can be treated as a slowmemory or peripheral and utilize a technique to extend thewrite strobe. A simple extension of the write time, by addinga wait state, can simultaneously hold the write strobe activeand data valid on the bus to satisfy the minimum WR pulse-width. If this does not provide a sufficient data hold time atthe end of the write cycle, a negative edge triggeredone-shot can be included between the system write strobeand the WR pin of the DAC. This is illustrated in Figure 5 foran exemplary system which provides a 250ns WR strobetime with a data hold time of less than 10ns.
The proper data set-up time prior to the latching edge (LO toHI transition) of the WR strobe, is insured if the WR pulse-width is within spec and the data is valid on the bus for theduration of the DAC WR strobe.
1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digitalinputs are changing state, a narrow spike of current may flowout of the current output terminals. This spike is caused bythe rapid switching of internal logic gates that are respondingto the input changes.
There are several recommendations to minimize this effect.When latching data in the DAC, always use the input registeras the latch. Second, reducing the VCC supply for the DACfrom +15V to +5V offers a factor of 5 improvement in themagnitude of the feedthrough, but at the expense of internallogic switching speed. Finally, increasing CC (Figure 8) to avalue consistent with the actual circuit bandwidth require-ments can provide a substantial damping effect on any out-put spikes.
DS005608-7
ILE=LOGIC “1”; WR2 and XFER GROUNDED
FIGURE 4.
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DAC0830 Series Application Hints (Continued)
2.0 ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to pro-vide an accurate analog output quantity which is representa-tive of the applied digital word. In the case of the DAC0830,the output, IOUT1, is a current directly proportional to theproduct of the applied reference voltage and the digital inputword. For application versatility, a second output, IOUT2, isprovided as a current directly proportional to the complementof the digital input. Basically:
where the digital input is the decimal (base 10) equivalent ofthe applied 8-bit binary word (0 to 255), VREF is the voltageat pin 8 and 15 kΩ is the nominal value of the internal resis-tance, R, of the R-2R ladder network (discussed in Section2.1).
Several factors external to the DAC itself must be consid-ered to maintain analog accuracy and are covered in subse-quent sections.
2.1 The Current Switching R-2R Ladder
The analog circuitry, Figure 6, consists of a silicon-chromium(SiCr or Si-chrome) thin film R-2R ladder which is depositedon the surface oxide of the monolithic chip. As a result, thereare no parasitic diode problems with the ladder (as theremay be with diffused resistors) so the reference voltage,VREF, can range −10V to +10V even if VCC for the device is5VDC.
The digital input code to the DAC simply controls the positionof the SPDT current switches and steers the available laddercurrent to either IOUT1 or IOUT2 as determined by the logic in-
put level (“1” or “0”) respectively, as shown in Figure 6. TheMOS switches operate in the current mode with a small volt-age drop across them and can therefore switch currents ofeither polarity. This is the basis for the 4-quadrant multiplyingfeature of this DAC.
2.2 Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the ap-plied digital code, it is important that the voltages at both ofthe current output pins be as near ground potential (0VDC)as possible. With VREF=+10V every millivolt appearing at ei-ther IOUT1 or IOUT2 will cause a 0.01% linearity error. In mostapplications this output current is converted to a voltage byusing an op amp as shown in Figure 7.
The inverting input of the op amp is a “virtual ground” createdby the feedback from its output through the internal 15 kΩ re-sistor, Rfb. All of the output current (determined by the digitalinput and the reference voltage) will flow through Rfb to theoutput of the amplifier. Two-quadrant operation can be ob-tained by reversing the polarity of VREF thus causing IOUT1 toflow into the DAC and be sourced from the output of the am-plifier. The output voltage, in either case, is always equal toIOUT1xRfb and is the opposite polarity of the reference volt-age.
The reference can be either a stable DC voltage source oran AC signal anywhere in the range from −10V to +10V. TheDAC can be thought of as a digitally controlled attenuator:the output voltage is always less than or equal to the appliedreference voltage. The VREF terminal of the device presentsa nominal impedance of 15 kΩ to ground to external circuitry.
Always use the internal Rfb resistor to create an output volt-age since this resistor matches (and tracks with tempera-ture) the value of the resistors used to generate the outputcurrent (IOUT1).
DS005608-8
FIGURE 5. Accommodating a High Speed System
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DAC0830 Series Application Hints (Continued)
2.3 Op Amp Considerations
The op amp used in Figure 7 should have offset voltage null-ing capability (See Section 2.5).
The selected op amp should have as low a value of inputbias current as possible. The product of the bias currenttimes the feedback resistance creates an output voltage er-ror which can be significant in low reference voltage applica-tions. BI-FET™ op amps are highly recommended for usewith these DACs because of their very low input current.
Transient response and settling time of the op amp are im-portant in fast data throughput applications. The largest sta-bility problem is the feedback pole created by the feedbackresistance, Rfb, and the output capacitance of the DAC. Thisappears from the op amp output to the (−) input and includesthe stray capacitance at this node. Addition of a lead capaci-tance, CC in Figure 8, greatly reduces overshoot and ringingat the output for a step change in DAC output current.
Finally, the output voltage swing of the amplifier must begreater than VREF to allow reaching the full scale output volt-age. Depending on the loading on the output of the amplifierand the available op amp supply voltages (only ±12 volts inmany development systems), a reference voltage less than10 volts may be necessary to obtain the full analog outputvoltage range.
2.4 Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry canbe used to generate a bipolar output voltage from a fixed ref-erence voltage. This, in effect, gives sign significance to theMSB of the digital input word and allows two-quadrant multi-plication of the reference voltage. The polarity of the refer-ence can also be reversed to realize full 4-quadrant multipli-cation: ±VREFx±Digital Code=±VOUT. This circuit is shownin Figure 9.
This configuration features several improvements over exist-ing circuits for bipolar outputs with other multiplying DACs.Only the offset voltage of amplifier 1 has to be nulled to pre-serve linearity of the DAC. The offset voltage error of thesecond op amp (although a constant output voltage error)has no effect on linearity. It should be nulled only if absoluteoutput accuracy is required. Finally, the values of the resis-tors around the second amplifier do not have to match the in-ternal DAC resistors, they need only to match and tempera-ture track each other. A thin film 4-resistor network availablefrom Beckman Instruments, Inc. (part no. 694-3-R10K-D) isideally suited for this application. These resistors arematched to 0.1% and exhibit only 5 ppm/˚C resistance track-ing temperature coefficient. Two of the four available 10 kΩresistors can be paralleled to form R in Figure 9 and theother two can be used independently as the resistances la-beled 2R.
2.5 Zero Adjustment
For accurate conversions, the input offset voltage of the out-put amplifier must always be nulled. Amplifier offset errorscreate an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltageappearing at the DAC outputs as near 0VDC as possible.This is accomplished for the typical DAC — op amp connec-tion (Figure 7) by shorting out Rfb, the amplifier feedback re-sistor, and adjusting the VOS nulling potentiometer of the opamp until the output reads zero volts. This is done, of course,with an applied digital code of all zeros if IOUT1 is driving theop amp (all one’s for IOUT2). The short around Rfb is then re-moved and the converter is zero adjusted.
DS005608-37
FIGURE 6.
DS005608-38
FIGURE 7.
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DAC0830 Series Application Hints (Continued)
2.6 Full-Scale Adjustment
In the case where the matching of Rfb to the R value of theR-2R ladder (typically ±0.2%) is insufficient for full-scale ac-curacy in a particular application, the VREF voltage can beadjusted or an external resistor and potentiometer can beadded as shown in Figure 10 to provide a full-scale adjust-ment.
The temperature coefficients of the resistors used for this ad-justment are of an important concern. To prevent degrada-tion of the gain error temperature coefficient by the external
resistors, their temperature coefficients ideally would have tomatch that of the internal DAC resistors, which is a highly im-practical constraint. For the values shown in Figure 10, if theresistor and the potentiometer each had a temperature coef-ficient of ±100 ppm/˚C maximum, the overall gain error tem-perature coefficent would be degraded a maximum of0.0025%/˚C for an adjustment pot setting of less than 3% ofRfb.
DS005608-39
tsOP Amp C C (O to Full Scale)
LF356 22 pF 4 µs
LF351 22 pF 5 µs
LF357* 10 pF 2 µs
*2.4 kΩ RESISTOR ADDED FROM−INPUT TO GROUND TOINSURE STABILITY
FIGURE 8.
DS005608-40
Input Code IDEAL V OUT
MSB LSB +V REF −VREF
1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0
*THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS, INC. AS THEIR PART NO. 694-3-R10K-D
FIGURE 9.
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DAC0830 Series Application Hints(Continued)
2.7 Using the DAC0830 in a Voltage SwitchingConfiguration
The R-2R ladder can also be operated as a voltage switch-ing network. In this mode the ladder is used in an invertedmanner from the standard current switching configuration.
The reference voltage is connected to one of the current out-put terminals (IOUT1 for true binary digital control, IOUT2 is forcomplementary binary) and the output voltage is taken fromthe normal VREF pin. The converter output is now a voltagein the range from 0V to 255/256 VREF as a function of the ap-plied digital code as shown in Figure 11.
This configuration offers several useful application advan-tages. Since the output is a voltage, an external op amp isnot necessarily required but the output impedance of theDAC is fairly high (equal to the specified reference input re-sistance of 10 kΩ to 20 kΩ) so an op amp may be used forbuffering purposes. Some of the advantages of this modeare illustrated in Figures 12, 13, 14, 15.
There are two important things to keep in mind when usingthis DAC in the voltage switching mode. The applied refer-ence voltage must be positive since there are internal para-sitic diodes from ground to the IOUT1 and IOUT2 terminalswhich would turn on if the applied reference went negative.There is also a dependence of conversion linearity and gainerror on the voltage difference between VCC and the voltageapplied to the normal current output terminals. This is a re-sult of the voltage drive requirements of the ladder switches.To ensure that all 8 switches turn on sufficiently (so as not toadd significant resistance to any leg of the ladder andthereby introduce additional linearity and gain errors) it isrecommended that the applied reference voltage be keptless than +5VDC and VCC be at least 9V more positive thanVREF. These restrictions ensure less than 0.1% linearity andgain error change. Figures 16, 17, 18 characterize the ef-fects of bringing VREF and VCC closer together as well astypical temperature performance of this voltage switchingconfiguration.
DS005608-11
FIGURE 10. Adding Full-Scale Adjustment
DS005608-12
FIGURE 11. Voltage Mode Switching
DS005608-41
• Voltage switching mode eliminates output signal inver-sion and therefore a need for a negative power supply.
• Zero code output voltage is limited by the low level outputsaturation voltage of the op amp. The 2 kΩ pull-down re-sistor helps to reduce this voltage.
• VOS of the op amp has no effect on DAC linearity.
FIGURE 12. Single Supply DAC
www.national.com 14
DAC0830 Series Application Hints (Continued)
DS005608-42
FIGURE 13. Obtaining a Bipolar Output from a FixedReference with a Single Op Amp
DS005608-60
FIGURE 14. Bipolar Output with Increased Output Voltage Swing
www.national.com15
DAC0830 Series Application Hints (Continued)
DS005608-14
FIGURE 15. Single Supply DAC with Level Shift and Span-Adjustable Output
Gain and Linearity ErrorVariation vs. Supply Voltage
DS005608-32
Note: For these curves, VREF is the voltage applied to pin 11 (IOUT1) withpin 12 (IOUT2) grounded.
FIGURE 16.
Gain and Linearity ErrorVariation vs. Reference Voltage
DS005608-33
FIGURE 17.
www.national.com 16
DAC0830 Series Application Hints(Continued)
2.8 Miscellaneous Application Hints
These converters are CMOS products and reasonable careshould be exercised in handling them to prevent catastrophicfailures due to static discharge.
Conversion accuracy is only as good as the applied refer-ence voltage so providing a stable source over time and tem-perature changes is an important factor to consider.
A “good” ground is most desirable. A single point ground dis-tribution technique for analog signals and supply returnskeeps other devices in a system from affecting the output ofthe DACs.
During power-up supply voltage sequencing, the −15V (or−12V) supply of the op amp may appear first. This will cause
the output of the op amp to bias near the negative supply po-tential. No harm is done to the DAC, however, as the on-chip15 kΩ feedback resistor sufficiently limits the current flowfrom IOUT1 when this lead is internally clamped to one diodedrop below ground.
Careful circuit construction with minimization of lead lengthsaround the analog circuitry, is a primary concern. Good highfrequency supply decoupling will aid in preventing inadvert-ant noise from appearing on the analog output.
Overall noise reduction and reference stability is of particularconcern when using the higher accuracy versions, theDAC0830 and DAC0831, or their advantages are wasted.
3.0 GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input regis-ters are purposely omitted. Any of the control formats dis-cussed in Section 1 of the accompanying text will work withany of the circuits shown. The method used depends on theoverall system provisions and requirements.
The digital input code is referred to as D and represents thedecimal equivalent value of the 8-bit binary input, for ex-ample:
Binary Input D
Pin 13 Pin 7 Decimal
MSB LSB Equivalent
1 1 1 1 1 1 1 1 255
1 0 0 0 0 0 0 0 128
0 0 0 1 0 0 0 0 16
0 0 0 0 0 0 1 0 2
0 0 0 0 0 0 0 0 0
Gain and Linearity ErrorVariation vs. Temperature
DS005608-34
FIGURE 18.
www.national.com17
Applications
DAC Controlled Amplifier (Volume Control)
DS005608-43
Capacitance Multiplier
DS005608-44
Variable f O, Variable Q O, Constant BW Bandpass Filter
DS005608-17
www.national.com 18
Applications (Continued)
DAC Controlled Function Generator
DS005608-18
www.national.com19
Applications (Continued)
Two Terminal Floating 4 to 20 mA Current Loop Controller
DS005608-19
• DAC0830 linearly controls the current flow from the input terminal to the output terminal to be 4 mA (for D=0) to 19.94 mA (forD=255).
• Circuit operates with a terminal voltage differential of 16V to 55V.
• P2 adjusts the magnitude of the output current and P1 adjusts the zero to full scale range of output current.
• Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can flow-through (con-nect control lines to pins 3 and 10 of the DAC) and the input data can be set by SPST toggle switches to ground (pins 3 and10).
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.
2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.
National SemiconductorCorporationAmericasTel: 1-800-272-9959Fax: 1-800-737-7018Email: [email protected]
National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: [email protected]
National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507
www.national.com
Molded Chip Carrier (V)Order Number DAC0830LCV
or DAC0832LCVNS Package Number V20A
DA
C08
30/D
AC
0832
8-B
itµP
Com
patib
le,D
oubl
e-B
uffe
red
Dto
AC
onve
rters
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Features• Low input bias current• High input impedance• Wide gain bandwidth: 4 MHz Typ.• High slew rate: 13 V/µs Typ.
DescriptionThe LF347 is a high speed quad JFET input operationalamplifier. This feature high input impedance, widebandwidth, high slew rate, and low input offset voltage andbias current. LF347 may be used in circuits requiring highinput impedance. High slew rate and wide bandwidth, lowinput bias current.
14-DIP
1
14-SOP
1
Internal Block Diagram
LF347Quad Operational Amplifier (JFET)
LF347
2
Schematic Diagram(One Section Only)
Absolute Maximum RatingsParameter Symbol Value Unit
Supply Voltage VCC ±18 VDifferential Input Voltage VI(DIFF) 30 VInput Voltage Range VI ±15 VOutput Short Circuit Duration - Continuous -Power Dissipation PD 570 mWOperating Temperature Range TOPR 0 ~ + 70 °CStorage Temperature Range TSTG -65 ~ + 150 °C
LF347
3
Electrical Characteristics(VCC= +15V, VEE= -15V, TA=25 °C, unless otherwise specified)
Note :1. LF347 : 0≤TA≤+70 °C2. Guaranteed by design
Parameter Symbol ConditionsLF347
UnitMin. Typ. Max.
Input Offset Voltage VIORS = 10KΩ - 5 10
mVNote 1 - - 13
Input Offset Voltage Drift(Note2) ∆VIO/∆T RS = 10KΩ - 10 - µV/ °C
Input Offset Current IIO- 25 100 pA
Note 1 - - 4 nA
Input Bias Current IBIAS- 50 200 pA
Note 1 - - 8 nA
Large Signal Voltage Gain GVRL = 2KΩ 25 100 -
V/mVVO(P-P)= ±10V Note 1 15 - -
Output Voltage Swing VO(PP) RL = 10KΩ ±12 ±13.5 - V
Input Voltage Range VI(R) - ±11 +15-12 - V
Common-Mode Rejection Ratio CMRR RS ≤ 10KΩ 80 100 - dBPower Supply Rejection Ratio PSRR RS ≤ 10KΩ 80 100 - dBInput Resistance RI - - 1012 - ΩSupply Current ICC - - 7.2 11 mASlew Rate SR - - 13 - V/µSGain Bandwidth Product(Note2) GBW - - 4 - MHzChannel Seperation CS f = 1Hz ~ 20Khz
(input referenced) - 120 - dB
Equivalent Input NoiseVoltage eN
RS = 100Ωf = 1KHz - 20 - nV/
Equivalent Input NoiseCurrent IN f = 1KHz - 0.01 - pA/
Hz
Hz
LF347
4
Mechanical DimensionsPackage
Dimensions in millimeters
6.40 ±0.20
7.620.300
2.54
0.10
0
#1
#7 #8
#14
0.252 ±0.008
0~15°
0.25+0.10–0.05
0.010+0.004–0.002
3.30 ±0.30
0.130 ±0.012
3.25 ±0.20
0.128 ±0.008
19.4
0 ±0
.20
0.76
4 ±0
.008
19.8
00.
780
MA
X
5.080.200
0.200.008
MAX
MIN
2.08
0.08
2(
)
0.46
±0.
10
0.01
8 ±0
.004
0.05
9 ±0
.004
1.50
±0.
10
14-DIP
LF347
5
Mechanical Dimensions (Continued)
Package Dimensions in millimeters
8.56
±0.
20
0.33
7 ±0
.008
1.27
0.05
0
5.720.225
1.55 ±0.10
0.061 ±0.004
0.050.002
6.00 ±0.30
0.236 ±0.012
3.95 ±0.20
0.156 ±0.008
0.60 ±0.20
0.024 ±0.008
8.70
0.34
3M
AX
#1
#7 #8
0~8°
#14
0.47
0.01
9(
)
1.800.071
MA
X0.
10M
AX
0.00
4
MAX
MIN
+0.
10-0
.05
0.20
+0.
004
-0.0
020.
008
+0.
10-0
.05
0.40
6
+0.
004
-0.0
020.
016
14-SOP
LF347
6/1/01 0.0m 001Stock#DSxxxxxxxx
2001 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Ordering InformationProduct Number Package Operating Temperature
LF347N 14-DIP0 ~ + 70°C
LF347M 14-SOP
DATA SHEET
Product specificationSupersedes data of 1997 Jun 03File under Discrete Semiconductors, SC04
1997 Sep 03
DISCRETE SEMICONDUCTORS
BC107; BC108; BC109NPN general purpose transistors
M3D125
1997 Sep 03 2
Philips Semiconductors Product specification
NPN general purpose transistors BC107; BC108; BC109
FEATURES
• Low current (max. 100 mA)
• Low voltage (max. 45 V).
APPLICATIONS
• General purpose switching and amplification.
DESCRIPTION
NPN transistor in a TO-18; SOT18 metal package.PNP complement: BC177.
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT w
mm 5.314.74
0.470.41
5.455.30
4.704.55
1.030.94
1.10.9
15.012.7
α
0.40 45°
A a b D D1 j k L
2.54
1997 Sep 03 6
Philips Semiconductors Product specification
NPN general purpose transistors BC107; BC108; BC109
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of theseproducts can reasonably be expected to result in personal injury. Philips customers using or selling these products foruse in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from suchimproper use or sale.
Data Sheet Status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ormore of the limiting values may cause permanent damage to the device. These are stress ratings only and operationof the device at these or at any other conditions above those given in the Characteristics sections of the specificationis not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1997 Sep 03 7
Philips Semiconductors Product specification
NPN general purpose transistors BC107; BC108; BC109
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825