Spring 2014, Mar 17 . . . Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design ELEC 7770: Advanced VLSI Design (Agrawal) (Agrawal) 1 ELEC 7770 ELEC 7770 Advanced VLSI Design Advanced VLSI Design Spring 2014 Spring 2014 Zero Zero - - Skew Clock Routing Skew Clock Routing Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor ECE Department, Auburn University ECE Department, Auburn University Auburn, AL 36849 Auburn, AL 36849 [email protected]http://www.eng.auburn.edu/~vagrawal/COURSE/ http://www.eng.auburn.edu/~vagrawal/COURSE/ E7770_Spr14/course.html E7770_Spr14/course.html
23
Embed
Spring 2014, Mar 17...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Zero - Skew Clock Routing Vishwani D. Agrawal.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11
A. L. Fisher and H. T. Kung, “Synchronizing Large A. L. Fisher and H. T. Kung, “Synchronizing Large Systolic Arrays,” Systolic Arrays,” Proc. SPIEProc. SPIE, vol. 341, pp. 44-52, May , vol. 341, pp. 44-52, May 1982.1982.
A. Kahng, J. Cong and G. Robins, “High-Performance A. Kahng, J. Cong and G. Robins, “High-Performance Clock Routing Based on Recursive Geometric Clock Routing Based on Recursive Geometric Matching,” Matching,” Proc. Design Automation ConfProc. Design Automation Conf., June ., June 1991, pp. 322-327.1991, pp. 322-327.
M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock Routing for High-Performance IC’s,” Routing for High-Performance IC’s,” Proc. Design Proc. Design Automation ConfAutomation Conf., June 1990, pp. 573-579.., June 1990, pp. 573-579.
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 44
Zero-Skew RoutingZero-Skew Routing Build clock tree bottom up:Build clock tree bottom up:
Leaf nodes are all equal loading flip-flops.Leaf nodes are all equal loading flip-flops. Two zero-skew subtrees are joined to form a larger zero-skew Two zero-skew subtrees are joined to form a larger zero-skew
subtree.subtree. Entire clock tree is built recursively.Entire clock tree is built recursively.
J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal Delay in RC Tree Networks,” Delay in RC Tree Networks,” IEEE Trans. CADIEEE Trans. CAD, vol. 2, , vol. 2, no. 3, pp. 202-211, July 1983.no. 3, pp. 202-211, July 1983.
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 55
Balancing Subtrees (1)Balancing Subtrees (1)
t1
C1c1/2c1/2
t2
C2c2/2c2/2
r1
r2(1 – x)L
xL
Tapping point
Subtree 1
Subtree 2
A
B
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 66
Balancing Subtrees (2)Balancing Subtrees (2)
Subtrees 1 and 2 are each balanced (zero-Subtrees 1 and 2 are each balanced (zero-skew) trees, with delays t1 and t2 to respective skew) trees, with delays t1 and t2 to respective leaf nodes.leaf nodes.
Total capacitances of subtrees are C1 and C2, Total capacitances of subtrees are C1 and C2, respectively.respectively.
Connect points A and B by a minimum-length Connect points A and B by a minimum-length wire of length L.wire of length L.
Determine a tapping point x such that wire Determine a tapping point x such that wire lengths xL and (1 – x)L produce zero skew.lengths xL and (1 – x)L produce zero skew.
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 77
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 99
Example 1Example 1
FF
FF
FF
FF
FF
FF
FFTo next level
Subtree 1
Subtree 2
0.7
74
45m
m
0.2555mm
t1 = 5ps, C1 = 3pFt1 = 5ps, C1 = 3pF
t2 = 10ps, C2 = 6pFt2 = 10ps, C2 = 6pF
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1010
Balancing Subtrees, x > 1Balancing Subtrees, x > 1 Tapping point set at root of tree with larger loading (C2, t2).Tapping point set at root of tree with larger loading (C2, t2). Wire to the root of other tree is elongated to provide Wire to the root of other tree is elongated to provide
additional delay. Wire length L is found as follows:additional delay. Wire length L is found as follows: Set x = 1 in Set x = 1 in abLabL22x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2)x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2)
i.e., Li.e., L22 + (2C1/b)L – 2.9 (t2 – t1)/(ab) = 0 + (2C1/b)L – 2.9 (t2 – t1)/(ab) = 0 Wire length is given by:Wire length is given by:
For a wire of 1.735mm length, place the clock feed at one end.For a wire of 1.735mm length, place the clock feed at one end.
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1313
Example 2, L = 1.735mm Example 2, L = 1.735mm
FF
FF
FF
FF
FF
FF
FF
To next level
Subtree 1
Subtree 2
L = 1.7355mm
t1 = 2ps, C1 = 1pFt1 = 2ps, C1 = 1pF
t2 = 15ps, C2 = 10pFt2 = 15ps, C2 = 10pF
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1414
Balancing Subtrees, x < 0Balancing Subtrees, x < 0 Tapping point set at root of tree with smaller loading (C1, t1).Tapping point set at root of tree with smaller loading (C1, t1). Wire to the root of other tree is elongated to provide Wire to the root of other tree is elongated to provide
additional delay. Wire length L found as follows:additional delay. Wire length L found as follows: Set x = 0 in Set x = 0 in abLabL22x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2)x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2)
i.e., Li.e., L22 + (2C2/b)L – 2.9 (t1 – t2)/(ab) = 0 + (2C2/b)L – 2.9 (t1 – t2)/(ab) = 0 Wire length is given by:Wire length is given by:
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2121
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2222
Optimized Skew DesignOptimized Skew Design
FF A FF BComb.
CKT = 66.67ns
FF CComb.
Delay=75ns
Delay= 50ns
8.33ns 16.67ns 0nsDelay
Comb. Delay=75ns
Spring 2014, Mar 17 . . .Spring 2014, Mar 17 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2323
ConclusionConclusion
Zero-skew design is possible at the layout level.Zero-skew design is possible at the layout level. Zero-skew usually results in higher clock speed.Zero-skew usually results in higher clock speed. Nonzero clock skews can improve the design Nonzero clock skews can improve the design