Spartan-3E

Spartan-3E

Presentation by : Nilesh A. shah

(p08ec913)

Overview

• All Xilinx FPGAs contain the same basic resources– Slices (grouped into CLBs)

• Contain combinatorial logic and register resources– IOBs

• Interface between the FPGA and the outside world– Programmable interconnect – Other resources

• Memory• Multipliers• Global clock buffers• Boundary scan logic

Xilinx FPGA Architecture

• Logic Fabric– Gates and flip-flops

• Embedded Blocks – Memory– DSP/Multipliers – Clock management– High speed serial I/O– Soft/hard processors

• Programmable I/Os• In-system programmable

I3

I1

I2

I0

O

D Q

SET

RST

CE

D Q

SET

RST

CE0 1

I3

I1

I2

I0

O 0 1

Logic Fabric

• Logic Cell– Lookup table (LUT)– Flip-Flop– Carry logic– Muxes (not shown)

• Slice– Two Logic Cells

• Spartan-3E FPGAs– 2K to 33K logic cells

Memory

• Block RAM– RAM or ROM– True dual port

• Separate read and write ports– Independent port size

• Data width translation– Excellent for FIFOs

CLKA

DIPA

ADDRA

DOPA

CLKB

ADDRB

DIA DOA

DIPB DOPBDIB DOB

Multipliers

• 18 x 18 Multipliers– Signed or unsigned– Optional pipeline stage– Cascadable

18 bit

18 bit

36 bit

Clock Management

• Digital Clock Managers (DCMs)– Clock de-skew– Phase shifting– Clock multiplication – Clock division– Frequency synthesis

CLKIN CLK0

CLK90

CLKFX

Programmable I/Os

• Single-ended• Differential / LVDS• Programmable I/O standards

– Multiple I/O banks• DDR I/O registers• On-chip termination

Reg

Reg

DDR mux

3-State

Reg

Reg

DDR mux

PAD

Reg

Reg

Input

Output

I/O Banks

Advanced, Low-Cost Features of SPARTEN 3E

• Five devices with 100K to 16M system gates • From 66 to 376 I/Os with package and density migration • Up to 648 Kbits of block RAM and up to 231 Kbits of distributed RAM • Up to 36 embedded 18x18 multipliers for high performance DSP applications • Up to eight Digital Clock Managers

Xilinx Spartan-3E Family

36282012418x18 Multipliers

88442DCMs

136K

504K

304

19,512

1.2M

15K

72K

108

2,160

100K

33,19210,4765,508Logic Cells

648K360K216KBlock RAM bits

231K73K38KDistributed RAM bits

376232172Maximum I/O

1.6M500K250KGates

Device3S1200E 3S1600E3S500E3S250E3S100E

Spartan-3E CLB Resources

Available User I/Os and Differential (Diff) I/O Pairs

Spartan-3E Starter Kit

Spartan-3E Kit specific features

• Parallel NOR Flash configuration• MultiBoot FPGA configuration from Parallel NOR Flash PROM• SPI serial Flash configuration• MicroBlaze™ 32-bit embedded RISC processor• PicoBlaze™ 8-bit embedded controller• DDR memory interfaces• Four-output, SPI-based Digital-to-Analog Converter (DAC)• Two-input, SPI-based Analog-to-Digital Converter (ADC) with

programmable-gain pre-amplifier

Spartan-3E FPGA Board cont.

• Connectors and Interfaces– Ethernet – JTAG USB download – Two 9-pin RS-232 Serial Port, – PS/2- style mouse/keyboard port– rotary encoder with push button – Four Slide Switches – Eight Individual LED Outputs – Four Momentary-Contact Push Buttons – 100-Pin hirose Expansion Connection Ports– Three 6-pin expansion connectors

• Display: 16 character - 2 Line LCD

•A typical FPGA application uses a single non-volatile memory to store configurationimages. To demonstrate new Spartan-3E capabilities, the starter kit board has threedifferent configuration memory sources that all need to function well together. The extra configuration functions make the starter kit board more complex than typicalSpartan-3Eapplications.•The starter kit board also includes an on-board USB-based JTAG programming interface.The on-chip circuitry simplifies the device programming experience. In typical applications, the JTAG programming hardware resides off-board or in a separate programming module, such as the Xilinx Platform USB cable.

Voltages for all Applications:-The Spartan-3E Starter Kit board showcases a triple-output regulator developed by Texas Instruments, the TPS75003 specifically to power Spartan-3 and Spartan-3E FPGAs. This regulator is sufficient for most stand-alone FPGA applications. However, the starter kit board includes DDR SDRAM, which requires its own high-current supply. Similarly, the USB-based JTAG download solution requires a separate 1.8V supply.

Slide Switches Push-Button Switches

Rotary Push-Button Switch

Discrete LEDs

Available Clock Inputs

On-Board 50 MHz Oscillator

The Spartan-3E Starter Kit board supports a variety of FPGA configuration options:• Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the onboard USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD.• Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then configure the FPGA from the image stored in the Platform Flash PROM using Master Serial mode.• Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode.• Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI Down configuration modes. Further, an FPGA application can dynamically load two different FPGA configurations using the Spartan-3E FPGA’s MultiBoot mode.

FPGA Configuration Options

Detailed Configuration OptionsConfiguration Mode Jumper Settings

Two-Channel Analog Capture Circuit

DB15 VGA ConnectorDB9 Serial Port Connector

Digital-to-Analog Converter and Associated Header

DCE DTE

RJ-45 Ethernet Connector Expansion Headers

Xilinx Design Process

ImplementationConstraints

Silicon

Design Entry

Synthesis

Timing SimulationFloor-Planning

Behavioral Simulation

Timing Analysis

SynthesisConstraints

•Place & Route•Map•Translate

Implementation

Thank you QUESTION???