Shunt-LDO testing Laura Gonella, M. Barbero, H. Krueger 21/02/2010.

Shunt-LDO testing

Laura Gonella, M. Barbero, H. Krueger21/02/2010

LG - FE-I4 testing meeting - 21/02/2011

Shunt-LDO reminderCombination of a LDO and a shunt

transistor

Shunt regulation circuitry const IloadLDO regulation loop constant Vout

+ -

+

-

+

-

Iin

Iout

Vref

Vout

A1

A2

A3

M1M2

M3

M4

M5

R1

R2

Vin

Iload

R3

M6

Ishunt

Shunt-LDO: simplified schematic

LDO compensates Vout difference

VOUT1

VS1 VS2

VOUT2RL1 RL2

Isupply

Isupply

RS1 RS2

I1 I2

VOUT1+VS1=VOUT2+VS2

VOUT1 > VOUT2

VS1 < Vs2

2 Shunt-LDOs in parallel:

equivalent circuit

Shunt-LDO can be placed in parallel without problems due to mismatch Shunt-LDO with different Vout can be placed in parallel Shunt-LDO can cope with increased Iin Normal LDO operation when shunt circuitry is off

LG - FE-I4 testing meeting - 21/02/2011

Shunt-LDO in FEI4 2 shunt-LDO regulators in FEI4

Reg1 input connected to DC-DC output Reg2 independent

Biasing currents generated internally

Vref has to be provided externally Rint, Rext, and VDDShunt

connection selected externally to configure the device as Shunt-LDO or LDO

Reg2 Reg1

LDO Shunt-LDO with Rint Shunt-LDO with Rext

LG - FE-I4 testing meeting - 21/02/2011

Test board Modified FE-I4 SCC allows testing of

Both regulators, independently or in parallel FE-I4 with direct powering or Shunt-LDO/LDO powering

Reduced FE-I4 testing capability (wafer level testing)

External load

Vref1Vref2

Iin1 measureme

nt

Iin2 measureme

nt

Current input

Rint, Rext, VDDShunt

Vbp measurement1 VDDD

1 VDDA1 GND

LG - FE-I4 testing meeting - 21/02/2011

Test setup

For Shunt-LDO characterization Labview software developed by D. Arutinov for Shunt-LDO prototype testing Iin and Iload provided by programmable Keithley sourcemeter Vin, Vout, Vref/Vbp measured automatically using Keithley multimeters

For FE-I4 characterization USBPix

LG - FE-I4 testing meeting - 21/02/2011

Test plan

Tests both regulators in FE-I4 as Shunt-LDO and pure LDO

Test the 2 Shunt-LDO regulators in parallel Test FE-I4 with Shunt-LDO/LDO powering Test assemblies with Shunt-LDO/LDO powering

New card needed

LG - FE-I4 testing meeting - 21/02/2011

Reg2: Shunt-LDO

Output voltage is generated as soon as all transistors saturate A few unexpected features, which however do not harm the

regulator operation Second jump at higher Iin Vout < 2Vref, and decreases with increasing Iin

I show results with Rint. Those with Rext are the same.

Voltage generation

LG - FE-I4 testing meeting - 21/02/2011

Vin generation: second jump Depends on Vout

1.2V: @0.220A , 1.3V: @0.270A, 1.4: @0.330A, 1.5: @0.390A Investigation of biases: VDDShunt

Connected to Vin Bias for A3 and for the biasing circuitry Tried to set it to a constant value or connect to Vout

→ no effect on second jump Temperature effect?

Tried to cool board during test → no effect on second jump

More investigation needed Could it be a board feature?

LG - FE-I4 testing meeting - 21/02/2011

Vin generation: Vout value and behavior

Hypothesis: Vdrop on the ground line which effectively decreases the Vref Vref is referred to the board gnd,

whilst Vout is measured wrt the chip gnd

Measurement of gnd difference between chip gnd and board gnd

Results show that this hypothesis is valid after the second jump

Iin Vout meas Vout calc DeltaV calc GND difference0.170 1.422 1.528 0.106 0.0320.180 1.423 1.528 0.105 0.0340.190 1.423 1.528 0.105 0.0360.200 1.421 1.528 0.107 0.0380.210 1.420 1.528 0.108 0.0400.220 1.417 1.528 0.111 0.0420.230 1.415 1.528 0.113 0.0440.240 1.413 1.528 0.115 0.0460.250 1.410 1.528 0.118 0.0480.260 1.407 1.528 0.121 0.0500.270 1.404 1.528 0.124 0.0520.280 1.401 1.528 0.127 0.0540.290 1.397 1.528 0.131 0.0560.300 1.394 1.528 0.134 0.0600.310 1.390 1.528 0.138 0.0620.320 1.386 1.528 0.142 0.0640.330 1.383 1.528 0.145 0.0660.340 1.380 1.528 0.148 0.0680.350 1.377 1.528 0.151 0.0700.360 1.375 1.528 0.153 0.0720.370 1.374 1.528 0.154 0.0740.380 1.374 1.528 0.154 0.0760.390 1.448 1.530 0.082 0.0740.400 1.446 1.530 0.084 0.0760.410 1.443 1.530 0.087 0.0780.420 1.440 1.530 0.090 0.0800.430 1.438 1.530 0.092 0.0840.440 1.435 1.530 0.095 0.0860.450 1.432 1.530 0.098 0.0880.460 1.430 1.530 0.100 0.0900.470 1.428 1.532 0.104 0.0920.480 1.425 1.532 0.107 0.094

LG - FE-I4 testing meeting - 21/02/2011

Reg2: Shunt-LDO

Output voltage is stable for increasing Iload Input and output voltage collapse when Iload = Iin

Load regulationIin = 0.480A

LG - FE-I4 testing meeting - 21/02/2011

Reg2: LDO

Also for the LDO the voltage generation works fine

Again, Vout ≠ 2Vref

Voltage generation

LG - FE-I4 testing meeting - 21/02/2011

Reg1

Need to configure the DC-DC regulator properly Connect DC-DC input to Vin Power the LVDS receivers in FE-I4 to set the AUX-CLK (i.e. the internal

switches) to a defined set to avoid connection between DC-DC output and GND

Once the DC-DC is properly configured the Reg1 behaves as Reg2

At first the DC-DC regulator was left floating and the results did not look good...

Vin and Vout collapse at certain value of Iin/Iload

→ The current is not flowing in the Shunt-LDO but somewhere else...

LG - FE-I4 testing meeting - 21/02/2011

Reg1 resultsShunt-LDO

Voltage generation Load regulation

LDOVoltage regulation

LG - FE-I4 testing meeting - 21/02/2011

Conclusion Both regulators have been operated

Operation of Reg1 requires proper configuration of the DC-DC

Voltage generation and load current regulation are fine Still to understand second jump in voltage generation

characteristic and Vout value and behavior -> no show stopper Some investigations have been done already, need to think about it a bit

more Also, compare with results on LDO. In this case only the voltage regulation

loop is used

First results are encouraging. Characterization goes on...