Fabian Hügging – University of Bonn – February - 16 - 20111 WP3: Post processing and 3D Interconnection M. Barbero, L. Gonella, F. Hügging, H. Krüger and.

Fabian Hügging – University of Bonn – February - 16 - 20111

WP3: Post processing and 3D Interconnection

M. Barbero, L. Gonella, F. Hügging, H. Krüger and N. Wermes

AIDA Kick-Off MeetingCERN, 16-02-2011 – 18-02-2011

Fabian Hügging – University of Bonn – February - 16 - 20112

Introduction

• Post processing and 3D Interconnection – many possibilities e.g. material reduction of futures

trackers.• Vendors offer new processes:

– Through silicon Vias– Thinning of IC, sensors– 3D connection within CMOS– mirco bump bonding– etc.

• Bonn - IZM Berlin: long term relationship – main bump bonding vendor for ATLAS Pixel– development of new pixel module concepts– started 3 years with TSV and thin chips bump bonding

Fabian Hügging – University of Bonn – February - 16 - 20113

Current ATLAS Pixel Modules

• Material is an issue in trackers for HEP experiments for both radiation length and space issues:– In the present ATLAS pixel detector modules the FE (190µm thick)

accounts for 0.26% of X0

– Material introduced by services: wings, module flex, connectors: • Using the IBL as an example (note: TSV will not be used for the IBL!): Al flex +

wire bonds + pass. comp.: ~0.13%of X0

IBL module FE-I4

Fabian Hügging – University of Bonn – February - 16 - 20114

Advanced Pixel Module Concepts

Power Flex

Data Flex

EoS

FE-Chip

Sensor

pass. componentsTSVstapered

backside metal lines on ICs

HV?

Thin chip bump bonding and Through Silicon Vias required!

Fabian Hügging – University of Bonn – February - 16 - 20115

Thin chip bump bonding

1x1 FE-I3, 190µmok

2x3 FE-I3 (FE-I4 size), 190µmnot ok

2x3 FE-I3 (FE-I4 size),

300µmnot

sufficient

Current flip chip technique: IZM solder SnAg• Chip bow during flip chip

– Due to CTE mismatch between Si bulk and metals

– ~ 1/d3, d = chip diagonal• New techniques using handle-wafers

during flip chip and lift-off after flip chipping are needed– 3 methods studied so far with IZM Berlin

7.4mm

11.1 mm

FE-I3

20.2mm

16.8 mm

FE-I4

FE-I3 FE-I3

FE-I3 FE-I3

FE-I3 FE-I3

~ peak temp. of reflow process

190µm thick 0.26% X0

Bow profile along a diagonal

350 - 400µm thick ~0.5% X0

15µm

Fabian Hügging – University of Bonn – February - 16 - 20116

First investigations and problems

• First two methods used resp. a wax and a Brewer glue for carrier bonding

• Not successful– thinning ok, but chips bent up at the

corners, opposite to the End Of Column region

– Bump bonds do not connect in this area ATLAS pixel module with 90 µm thick FE-I2

1st method: wax

open bumps at the corner of the FE

2x2 FE-I3 array = 66% FE-I4, 90 µm, on dummy sensor

2nd method: Brewer glue

w/ carrier chip

w/o carrier chip

Fabian Hügging – University of Bonn – February - 16 - 20117

Polyimide method

90 µm

90 µm

Glass carrier on Si testchip before

laser exposure_25x

Glass carrier on Si testchip after

laser exposure_25x

thinning of FE wafer

Mounting on glass carrier wafer using polyimide glue

Bumping process on FE frontside

Dicing of FE wafer and carrier wafer package

FE flip chip bonding to sensor tile

Laser exposure of chip backside

Carrier chip detach

Process steps:

2x2 FE-I2 array, 90um, on dummy sensor

Cross section cut of first column all bumps are connected!

Fabian Hügging – University of Bonn – February - 16 - 20118

Results of electrical tests

All bumps connected in “critical” area…

..and across the chip

Some disconnected bumps close to the End of Column region Handling problems during wire bonding

Normal threshold behavior = unconnected bumps

Polyimide method works. Chosen thinning method for the FE-I4 thin chip modules prototyping program FE-I4 will be 16.8 x 20.2mm2, ~100 – 200 µm thick

Fabian Hügging – University of Bonn – February - 16 - 20119

Module concepts with TSV

• TSV allows routing of signals on the FE backside direct connection of service flex on FE backside (e.g. via wire bonding) – Less material: no need for wings, module flex, connectors

• Using the IBL as an example : ~0.13%X0– Easy interconnection scheme

• 2 processes @ IZM Berlin: Straight Side Walls and Tapered Side Walls TSVs– Both working, tapered side walls TSVs faster process

ATLAS pixel module with 90µm thick FE-I2 and tapered TSVs with simple backside metallization

FE-Chip

Sensor

pass. comp.TSVs backside metal lines on FE

flex

FE backsideView from

top

Stave top viewSingle chip modules

(cont…)

(… from End of Stave …)

bonding area actually connectedflex

bonding area

pads

Fabian Hügging – University of Bonn – February - 16 - 201110

Through Silicon Vias at IZM

• Thin chips are mandatory for Through Silicon Vias (TSV)!

• The process is a Via Last process done in two steps:– Via etching on the backside

• Bonding to carrier wafer (1)• Thinning of the backside (2)• Via etching (3) → stops at oxide layer• Oxide deposition on via walls (4)• Deposition of metal seed on via walls (5)• Via filling (6)• Structuring of the back side (7)• Carrier wafer is detached using moderate

heating (7-8)• Via etching from the frontside (8)

– In our case we just use the FE-chip as FEOL (no BEOL) and flip chip to the sensor afterwards.

• IZM offers two Via Last TSV processes– Straight Side Wall Vias– Tapered Side Wall Vias

SiO2

pads

Si (FEOL)

Si (BEOL)

FE wafer cross-section (not to scale)

(1) (2)

(3) (4)

(5) (6)

(7) (8)

Fabian Hügging – University of Bonn – February - 16 - 201111

Straight Side Wall TSV on Monitor Wafer

Backside Redistribution with

Probe pads

Via Filling

Si Etching

• Via etching though silicon wafer works well• The process is rather time consuming

– The via is etched and passivated in steps → Bosch process

Fabian Hügging – University of Bonn – February - 16 - 201112

Si Etch on Monitor Wafer until Oxide Layer

• Via bottom shape optimization – Clearly defined via edges, konvex via bottom shape– Still etch diameter inhomgenities on via bottom across the wafer

Left – 40µm

Front side view through temporary glass carrier wafer

Back side view into Si viaCenter – 71µm Right – 58µm

Fabian Hügging – University of Bonn – February - 16 - 201113

TSV etching with Tapered Side Walls

• Faster process – Vias are etched in one step and after

oxide is depositied• Walls are not straight

– Side wall angle 72°– Si thickness 77µm

• Max 100µm given the aspect ratio of the process

• Higher Si thickness possible with straight side wall TSV

– Via diameter on bottom 41µm– Via diameter on top 95µm

• The bigger via diameter on the top is not a problem if the FE-chip is thin enough. – It normally fits in the pad dimension on

the back side

Fabian Hügging – University of Bonn – February - 16 - 201114

Signals Routing on Backside and Flex

FEI4 Backside

bonding area

pads

d<1500μm

(cont…)

(… from End of Stave …)

bonding area actually connected

Example: Single chip option

Fabian Hügging – University of Bonn – February - 16 - 201115

Ongoing

Tapered TSVs processing on ATLAS FE-I2 batch

Tapered side walls TSV Backside redistribution

Bump deposition and dicing

Al pad opening by wet etching

Cu electroplating – interconnection plug to Al

pad

BEOL SiO2 stack etching

Front side processing

Back side processing

Thin chip!90µm

Done Final step

Process demonstrated on Monitor- and ATLAS FE-I Wafer Prototyping of an ATLAS pixel module with 90µm thin FE-I2, Tapered TSVs, and simple backside metallization is ongoing with IZM Berlin. First samples expected in 04/2011

Fabian Hügging – University of Bonn – February - 16 - 201116

3D Tezzaron-Chartered

• Milestones of 3D electronics:– 2D Chartered based on

FE-I4 prototype (analog tier) in 2009

– 3D Chartered-Tezzaron submitted in 2009

• 2D back in 2010• 3D still to come

– plan for full FE-I4 in 3D in 2012

• collaboration with CPPM

M5M4M3M2M1

M6

SuperContact

M1M2M3M4M5

M6

SuperContact

Bond Interface

Tie

r 2-

Dig

ital

Tie

r 1 -

An

alo

g(t

hin

ned

w

afe

r)

Back Side Metal

sensor

Sensor layout :Anna Macchiolo, MPI Munich

Fabian Hügging – University of Bonn – February - 16 - 201117

Summary

• Bonn contributions to WP3:– demonstrate a pixel

module with FE-I3/4 in 2-3 years:

• Through Silicon Vias• Thin FE chips• backside re-routing of

signals– Bonn contribution to 3D

electronics:• further participation in

3D Tezzaron-Chartered Consortium

• design of digital tier based on FE-I4

• go to full 3D FE-I4

14 by 61 pixels

layout of digital tier