Real Time Embedded Systems Finite State Machines Presented by: Hussein Bin Sama &&Tareq Alawneh Supervisor: Dr.Lo`ai Tawalbeh.

Real Time Embedded SystemsReal Time Embedded Systems

Finite State Machines

Presented by:

Hussein Bin Sama && Tareq Alawneh

Supervisor: Dr.Lo`ai Tawalbeh


Outlines

FSM Introduction.

FSM Design.

VHDL Design of FSM.

FSM minimization.

Case Study.


FSM definition

Finite state machine (FSM)

FSM is a model of behavior composed of a finite number of states, transitions between those states, and actions.


Concept of the State Machine

Computer Hardware = Datapath + Control

RegistersCombinational Functional Units (e.g., ALU)Busses

FSM generating sequences of control signalsInstructs datapath what to do next

Datapath status

Control

Control

Datapath

State

ControlSignalOutputs

Datapathstatus


Mealy vs. Moore State Machines

Finite State Machines (FSM) are of two types:

Moore Machines Next State = Function(Input, Present

State) Output = Function(Present State)

Mealy Machines Next State = Function(Input, Present

State) Output = Function(Input, Present State)


Moore FSM

Present StateRegister

Next StateFunction

(comb. logic)

OutputFunction

(comb. logic)

Inputs

Present StateNext State

Outputs

clock

reset

Output Is a Function of a Present State Only

state 1 /output 1

state 2 /output 2

transitioncondition 1

transitioncondition 2


Mealy FSM

Output Is a Function of a Present State and Inputs Next State

Function(comb. logic)

OutputFunction

(comb. logic)

Inputs

Present StateNext State

Outputs

Present StateRegister

clock

reset

state 1 state 2

transition condition 1 / output 1

transition condition 2 /output 2


Moore FSM - Example

Moore FSM that Recognizes Sequence “10”

S0 / 0 S1 / 0 S2 / 1

00

0

1

11

reset


Mealy FSM - Example

Moore FSM that Recognizes Sequence “10”

S0 S1

0 / 0 1 / 0 1 / 0

0 / 1reset


Moore and Mealy Machines

States vs. Transitions

Mealy Machine typically has fewer states than Moore Machine for same output sequence

Same I/O behavior

Different # of states

1

1

0

1

2

0

0

[0]

[0]

[1]

1/0

0

1

0/0

0/0

1/1

1

0


Finite State Machine Word Problems

Finite String Pattern Recognizer A finite string recognizer has one

input (X) and one output (Z ).The output

is asserted whenever the input sequence …010…has been observed, as long as the sequence 100 has never been seen.


Finite State Machine Word Problems

Step 1. Understanding the problem statement

Sample input/output behavior:

X: 00101010010Z: 00010101000

X: 11011010010Z: 00000001000


Finite State Machine Word ProblemsFinite String Recognizer

Step 2. Draw State Diagrams for the strings that must be recognized. I.e., 010 and 100.

Moore State DiagramReset signal places FSM in S0

Outputs 1 Loops in State

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0

1

0 0

0

1

0,1



Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = ..01 (state S2)

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0 1

1

…01

0

…010

0

…100

0,1

01

0


Finite State Machine Word ProblemsExit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0

Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0

0

1

1

…1

0

0

0,1

…100

0

…010

0 1

…01

…01



S2, S5 with incomplete transitions

S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case!

S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case!



Final State Diagram

S0 [0]

S1 [0]

S2 [0]

S3 [1]

S4 [0]

S5 [0]

S6 [0]

Reset

0

0

1

1

…1

0

0

0,1

…100

0

…010

0 1

…01

…011

1

..10


FSM Design

Six Step Process1.Understand the statement of the

Specification.2.Obtain an abstract specification of

the Synchronous Sequential Circuits (SSC).

3.Generate State Table.4.Perform state minimization.5.Choose FF types to implement

SSC state register.6.Implement the SSC.


Vending Machine Example



Example: Vending Machine SSC

General Machine Concept:

deliver package of gum after 15 cents deposited

single coin slot for dimes, nickels

no change

Block Diagram

Step 1. Understand the problem:

Vending Machine

SSC

N

D

Reset

Clk

OpenCoin

SensorGum

Release Mechanism

Draw a picture!

Nickel = 5 centsDime = 10 cents

Machine needs 15 cents to open



Tabulate typical input sequences:three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dime

Draw state diagram:

Inputs: N, D, reset

Output: open

Step 2. Map into more suitable abstract representation

Reset

N

N

N

D

D

N D

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

Nickel = 5 centsDime = 10 cents

Machine needs 15 cents to open

Initial Design



Step 3: State Minimization

Symbolic State Table

Reset

N

N

N , D

[open]

D

A

B

C

D

D

Present State

A B

C

D

D

0 0 1 1 0 0 1 1 0 0 1 1 X

N

0 1 0 1 0 1 0 1 0 1 0 1 X

Inputs Next State

A BC

X BCD

X CD

DX D

Output Open

0 0 0 X 0 0 0 X 0 0 0 X 1

Minimized Design

Merge States which have the same output

S0=AS1=BS2+S3 = CS4+S5+S6+S7+S8 = D



Step 4: State EncodingNext State

Q +1 Q+ 0

0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X

Present State Q 1 Q 0

0 0

0 1

1 0

1 1

D

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

N

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Inputs Output Open

0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X

State

A

B

C

D

NOTE!

For D-FFs the next state will be what is at the D input.

D1 D0



Step 5. Choose FFs for implementationD FF easiest to use

D1 = Q1 + D + Q0 N

D0 = N Q0 + Q0 N + Q1 N + Q1 D

OPEN = Q1 Q08 Gates

CLK

OPEN

CLK

Q 0

D

R

Q

Q

D

R

Q

Q

\ Q 1

\reset

\reset

\ Q 0

\ Q 0

Q 0

Q 0

Q 1

Q 1

Q 1

Q 1

D

D

N

N

N

\ N

D 1

D 0

Q1 Q0 00

D

D N

Q1

N

Q0

0 0 1 1

0 1 1 1

X X X X

1 1 1 1

01 11 10

00

01

11

10

Q1 Q0 00

D

D N

Q1

N

Q0

0 1 1 0

1 0 1 1

X X X X

0 1 1 1

01 11 10

00

01

11

10

Q1 Q0 00

D

D N

Q1

N

Q0

0 0 1 0

0 0 1 0

X X X X

0 0 1 0

01 11 10

00

01

11

10


VHDL Design of State Machines


FSM minimization Four steps for FSM minimization example.

Present State

Inputs

X=a X=b X=c

ABCDEF

E,1C,0B,1C,0A,0C,0

C,0F,1A,0F,1F,1E,1

B,1E,1D,1E,1B,1C,1

Next state , outputStep(1) Generate groups of states that generate the same output. This is called portions 1. P1 = ( A,C)

(B,D,E,F)


FSM minimization

Step(2) Create the following table based on step1 . Then generate

the next partitions P2

x Group #1

A C

Group #2

B D E F

a b c

2 21 1 2 2

1 1 1 12 2 2 22 2 2 1

P2 = (A C)(B D E)(F)Group

Number

Present State

Inputs

X=a X=b X=c

ABCDEF

E,1C,0B,1C,0A,0C,0

C,0F,1A,0F,1F,1E,1

B,1E,1D,1E,1B,1C,1

Next state , output


FSM minimization

Step(3) Create the following table based on step2 . Then generate the

next partitions P3

x Group #1

A C

Group #2

B D E

Group #3

F

a bc

2 21 1 2 2

1 1 1 3 3 3 2 2 2

121

P3 = (A C)(B D E)(F) = P2 Note: P2 = P3 then stop partitions and go to

step 4

Present State

Inputs

X=a X=b X=c

ABCDEF

E,1C,0B,1C,0A,0C,0

C,0F,1A,0F,1F,1E,1

B,1E,1D,1E,1B,1C,1

Next state , output


FSM minimization

New state name

Old state name

S1S2S3

(A,C)(B,D,E)

F

Present State

Inputs

X=a X=b X=c

S1S2S3

S2,1S1,0S1,0

S1,0S3,1S2,1

S2,1S2,1S1,1

Next state , output

Step(4) Renaming phase.

Present State

Inputs

X=a X=b X=c

ABCDEF

E,1C,0B,1C,0A,0C,0

C,0F,1A,0F,1F,1E,1

B,1E,1D,1E,1B,1C,1

Next state , output


Case Study: FSMD: finite-state machine with

datapath

GCD

(a) black-box view

x_i y_i

d_o

go_i

0: int x, y;1: while (1) {2: while (!go_i);3: x = x_i; 4: y = y_i;5: while (x != y) {6: if (x < y) 7: y = y - x; else 8: x = x - y; }9: d_o = x;}

(b) desired functionality

y = y -x7: x = x - y8:

6-J:

x!=y

5: !(x!=y)

x<y !(x<y)

6:

5-J:

1:

1

!1

x = x_i3:

y = y_i4:

2:

2-J:

!go_i

!(!go_i)

d_o = x

1-J:

9:

(c) state diagram

Steps : First create algorithm Convert algorithm to

“complex” state machine

Known as FSMD: finite-state machine with datapath

Example : ( greatest common divisor )


Creating the datapath

Create a register for any declared variable

Create a functional unit for each arithmetic operation

Connect the ports, registers and functional units

y = y -x7: x = x - y8:

6-J:

x!=y

5: !(x!=y)

x<y !(x<y)

6:

5-J:

1:

1

!1

x = x_i3:

y = y_i4:

2:

2-J:

!go_i

!(!go_i)

d_o = x

1-J:

9:

subtractor subtractor

7: y-x8: x-y5: x!=y 6: x<y

x_i y_i

d_o

0: x 0: y

9: d

n-bit 2x1 n-bit 2x1x_sel

y_sel

x_ld

y_ld

x_neq_y

x_lt_y

d_ld

<

5: x!=y

!=

Datapath


Creating the controller’s FSM

Same structure as FSMD

y = y -x7: x = x - y8:

6-J:

x!=y

5: !(x!=y)

x<y !(x<y)

6:

5-J:

1:

1

!1

x = x_i3:

y = y_i4:

2:

2-J:

!go_i

!(!go_i)

d_o = x

1-J:

9:

y_sel = 1y_ld = 1

7: x_sel = 1x_ld = 1

8:

6-J:

x_neq_y

5:!x_neq_y

x_lt_y !x_lt_y

6:

5-J:

d_ld = 1

1-J:

9:

x_sel = 0x_ld = 13:

y_sel = 0y_ld = 14:

1:

1

!1

2:

2-J:

!go_i

!(!go_i)

go_i

0000

0001

0010

0011

0100

0101

0110

0111 1000

1001

1010

1011

1100

Controller


7: y-x8: x-y5: x!=y 6: x<y

x_i y_i

d_o

0: x 0: y

9: d


y_sel

x_ld

y_ld

x_neq_y

x_lt_y

d_ld

<

5: x!=y

!=

Datapath


Splitting into a controller and datapath

y_sel = 1y_ld = 1

7: x_sel = 1x_ld = 1

8:

6-J:

x_neq_y=1

5:x_neq_y=0

x_lt_y=1 x_lt_y=0

6:

5-J:

d_ld = 1

1-J:

9:

x_sel = 0x_ld = 13:

y_sel = 0y_ld = 14:

1:1

!1

2:

2-J:

!go_i

!(!go_i)

go_i

0000

0001

0010

0011

0100

0101

0110

0111 1000

1001

1010

1011

1100

ControllerController implementation model

y_sel

x_selCombinational logic

Q3 Q0

State register

go_i

x_neq_y

x_lt_y

x_ld

y_ld

d_ld

Q2 Q1

I3 I0I2 I1


7: y-x8: x-y5: x!=y 6: x<y

x_i y_i

d_o

0: x 0: y

9: d


y_sel

x_ld

y_ld

x_neq_y

x_lt_y

d_ld

<

5: x!=y

!=

(b) Datapath


Optimizing the FSMD

Areas of possible improvements merge states

states with constants on transitions can be eliminated, transition taken is already known

states with independent operations can be merged


Optimizing the FSMD (cont.)

int x, y;

2:

go_i !go_i

x = x_iy = y_i

x<y x>y

y = y -x x = x - y

3:

5:

7: 8:

d_o = x9:

y = y -x7:

x = x - y8:

6-J:

x!=y

5: !(x!=y)

x<y !(x<y)

6:

5-J:

1:

1

!1

x = x_i

y = y_i4:

2:

2-J:

!go_i

!(!go_i)

d_o = x

1-J:

9:

int x, y;

3:

original FSMD optimized FSMD

eliminate state 1 – transitions have constant values

merge state 2 and state 2J – no loop operation in between them

merge state 3 and state 4 – assignment operations are independent of one another

merge state 5 and state 6 – transitions from state 6 can be done in state 5

eliminate state 5J and 6J – transitions from each state can be done from state 7 and state 8, respectively

eliminate state 1-J – transition from state 1-J can be done directly from state 9


Optimizing the datapath

Sharing of functional units if same operation occurs in different

states, they can share a single functional unit

Multi-functional units ALUs support a variety of operations, it

can be shared among operations occurring in different states


Optimizing the FSM

State minimization (As Discussed

Previously) task of merging equivalent states into a

single state state equivalent if for all possible input

combinations the two states generate the same outputs and transitions to the next same state


References

“Embedded Systems Design: A Unified Hardware/Software Introduction” Book Slides. Frank Vahid, Tony Givarrgis, Wiley, 2002

www.mwnl.snu.ac.kr/~schoi/Courses/201/Course_Materials

“Digital Design with CPLD Applications & VHDL” Book,Dueck , 2005

http://en.wikipedia.org/wiki/Finite_state_machine#Concepts_and_vocabulary

“Advanced Topic on Sequential Logic Design” handout.

Real Time Embedded Systems Finite State Machines Presented by: Hussein Bin Sama &&Tareq Alawneh Supervisor: Dr.Lo`ai Tawalbeh.

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