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Problems in VLSI design
• wire and transistor sizing
– signal delay in RC circuits– transistor and wire sizing– Elmore delay minimization via GP– dominant time constant minimization via SDP
• placement problems
– quadratic and ℓ1-placement– placement with timing constraints
1
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Signal delay in RC circuit
vin
1
0.5
vk
vin
Dkt = 0
Cdv
dt= −G(v(t) − 1), v(0) = 0
• capacitance matrix C = CT ≻ 0
• conductance matrix G = GT ≻ 0
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• v: node voltages
• as t → ∞, v(t) → 1
• delay at node k:
Dk = inf{T | vk(t) ≥ 0.5 for t ≥ T}
• critical delay: D = maxk Dk
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Transistor sizing
RC model of transistor
nMOS
transistor
(width w)
RC model (on)
RC model (off)
gate
drain
D
D
S
SG
Gsource
Rsd ∝ 1/w
Cd ∝ wCs ∝ wCg ∝ w
Cd ∝ wCs ∝ wCg ∝ w
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example
vout
CL
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• to first approximation: linear RC circuit
• design variable: transistor width w
• drain, source, gate capacitance affine in width
• ‘on’ resistance inversely proportional to width
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Wire sizing
interconnect wires in IC: distributed RC line
lumped RC model:ℓi
wi
Ci ∝ wiℓi Ci
Ri ∝ ℓi/wi
• replace each segment with π model
• segment capacitance proportional to width
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• segment resistance inversely proportional to width
• design variables: wire segment widths wi
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Optimization problems involving delay
C(x)dv
dt= −G(x)(v(t) − 1), v(0) = 0
• design parameters x: transistor & wire segment widths
• capacitances, conductances are affine in x:
C(x) = C0 + x1C1 + · · · + xmCm
G(x) = G0 + x1G1 + · · · + xmGm
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tradeoff between
• delay, complicated function of x
• area, affine in x
• dissipated power in transition v(t) = 0 → 1
1TC(x)1
2
affine in x
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Elmore delay
• area above step response
T elmk =
∫
∞
0
(1 − vk(t))dt
• first moment of impulse response
T elmk =
∫
∞
0
tvk(t)′dt
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replacements
vk
v′
k
Dk Dk T elmk
T elmk
1
0.5
• T elmk ≥ 0.5Dk
• good approximation of Dk only when vk is monotonically increasing
• interpret v′
k as probability density:Tk is mean, Dk is median
Problems in VLSI design 12
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Elmore delay for RC tree
RC tree
R1
R2 R3
R4
R5
R6
C1
C2 C3
C4 C5
C6
vin
1mr
2mr 3mr
4mr
5mr
6mr
• one input voltage source
• resistors form a tree with root at voltage source
• all capacitors are grounded
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Elmore delay to node k:
∑
i
Ci
(
∑
R’s upstream from node k and node i)
R1
R2 R3
R4
R5
R6
C1
C2 C3
C4 C6
C5
vin
1mr
2mr 3mr
4mr
5mr
6mr
Example:
T elm3 = C3(R1 + R2 + R3) + C2(R1 + R2) + C1R1
+ C4R1 + C5R1 + C6R1
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Elmore delay optimization via GP
in transistor & wire sizing, Ri = αi/xi, Cj = aTj x + bj
(αi ≥ 0, aj, bj ≥ 0)
Elmore delay:
T elmk =
∑
ij
γijRjCi =∑
k=1
βk
m∏
i=1
xαiki
(γij = +1 or 0, βk ≥ 0, αij = +1, 0,−1). . . a posynomial function of x ≻ 0
hence can minimize area or power, subject to bound on Elmore delay usinggeometric programming
commercial software (1980s): e.g., TILOS
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Limitations of Elmore delay optimization
• not a good approximation of 50% delay when step response is notmonotonic(capacitive coupling between nodes, or non-diagonal C)
• no useful convexity properties when
– there are loops of resistors– circuit has multiple sources– resistances depend on more than one variable
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Dominant time constant
C(x)dv
dt= −G(x)(v(t) − 1), v(0) = 0
• eigenvalues 0 > λ1 ≥ λ2 ≥ · · · ≥ λn given by
det(λiC(x) + G(x)) = 0
• solutions have formvk(t) = 1 −
∑
i
αikeλit
• slowest (“dominant”) time constant given by T dom = −1/λ1 (related todelay)
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−1/T dom
• can bound D, T elm in terms of T dom
• in practice, T dom is good approximation of D
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Dominant time constant constraint as linear matrix
inequality
upper bound T dom ≤ Tmax
−1/T dom
−1/Tmax
T dom ≤ Tmax ⇐⇒ TmaxG(x) − C(x) � 0
• convex constraint in x (linear matrix inequality)
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• no restrictions on G, C
• T dom is quasiconvex function of x, i.e., sublevel sets
{
x | T dom(x) ≤ Tmax
}
are convex
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Sizing via semidefinite programming
minimize area, power s.t. bound on T dom, upper and lower bounds on sizes
minimize fTx
subject to TmaxG(x) − C(x) � 0
xmini ≤ xi ≤ xmax
i
• a convex optimization problem (SDP)
• no restrictions on topology(loops of resistors, non-grounded capacitors)
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Wire sizing
minimize wire area subject to
• bound on delay (dominant time constant)
• bounds on segments widths
RC-model:
x1 x20
βxi βxiαxi
xi
Problems in VLSI design 22
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as SDP:minimize
∑
i
ℓixi
subject to TmaxG(x) − C(x) � 0
0 ≤ xi ≤ 1
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area-delay tradeoff
2 4 6 8 10 12 14 16 18200
400
600
800
1000
1200
1400
1600
1800
2000
AAAU
(a)AAAU
(b)AAAU
(c)
HHHY(d)
wire area
Tdom
0
0.5
1
0
0.5
1
0
0.3
0.6
0 2 4 6 8 10 12 14 16 18 200
0.2
• globally optimal tradeoff curve
• optimal wire profile tapers off
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step responses (solution (a))
0 200 400 600 800 1000 1200 1400 1600 1800 20000
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
time
voltag
e
��
��
T dom�
��
��
D
��
T elm
Problems in VLSI design 25
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Wire sizing and topology
x1 x2
x3
x4
x5
x6
βixi βixiαxi
xi
1m 2m 3m
4m
not solvable via Elmore delay minimization
min area s.t. max dominant time constant (via SDP):
minimize∑
xi
subject to TmaxG(x) − C(x) � 0
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tradeoff curve
0 0.1 0.2 0.3 0.4 0.5 0.6100
200
300
400
500
600
700
800
��
(a)
��
(b)
��
(c)
area
dom
inan
ttim
eco
nst
ant
• usually have more wires than are needed
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• solutions usually have some xi = 0
• different points on tradeoff curve have different topologies
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solution (a)
1m
4m
3m
x4 = 0.15 x6 = 0.11
0 100 200 300 400 500 600 700 800 900 10000
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1��
v1(t)� v4(t)@@I v3(t)
��T elm�
���
T dom
@@RD
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solution (b)
x4 = 0.03 x6 = 0.03
x3 = 0.02
1m 3m
4m0 100 200 300 400 500 600 700 800 900 1000
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1 ��v1(t)
� v4(t)@@I v3(t)
��T elm�
���
T dom
@@RD
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solution (c)
x3 = 0.014
1m 3m
4j
0 100 200 300 400 500 600 700 800 900 10000
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1 ��v1(t)
@@I v3(t)
��T elm�
���
T dom
@@RD
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Placement
• list of cells: cells i = 1, . . . , N are placeable, cellsi = N + 1, . . . , N + M are fixed (e.g., I/O)
• input and output terminals on boundary of cells
• group of terminals connected together is called a net
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• placement of cells determines length of interconnect wires, hence signaldelay
• problem: determine positions (xk, yk) for the placeable cells to satisfydelay constraints
• practical problem sizes can involve 100,000s of cells
• exact solution (including delay, area, overlap constraints) is very hard tocompute
• heuristics (often based on convex optimization) are widely used inpractice
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Quadratic placement
assume for simplicity:
• cells are points (i.e., have zero area)
• nets connect two terminals (i.e., are simple wires)
quadratic placement:
minimize∑
nets (i,j)
wij
(
(xi − xj)2 + (yi − yj)
2)
weights wij ≥ 0
unconstrained convex quadratic minimization(called ‘quadratic programming’ in VLSI)
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• solved using CG (and related methods) exploiting problem structure(e.g., sparsity)
• physical interpretation: wires are linear elastic springs
• widely used in industry
• constraints handled using heuristics(e.g., adjusting weights)
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ℓ1-placement
minimize∑
nets (i,j)
wij (|xi − xj| + |yi − yj|)
• measures wire length using Manhattan distance(wire routing is horizontal/vertical)
• motivation: delay of wire (i, j) is RC with
R = Rdriver + Rwire, C = Cwire + Cload
Rdriver, Cload are given, Rwire ≪ Rdriver,
Cwire ∝ wire length (Manhattan)
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Rdriver
Cwire Cload
• called ‘linear objective’ in VLSI
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Nonlinear spring models
minimize∑
nets (i,j)
h(|xi − xj| + |yi − yj|)
h convex, increasing on R+
example
z
h(z)
• flat part avoids ‘clustering’ of cells
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• quadratic part: for long wires Rwire ∝ length
• solved via convex programming
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Timing constraints
• cell i has a processing delay Dproci
• propagation delay through wire (i, j) is αℓij, where ℓij is the length ofthe wire
• minimize max delay from any input to any output
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Dproc1
Dproc2
Dproc3
Dproc4
Dproc5
ℓ14
ℓ13
ℓ23
ℓ35
ℓ45
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problem is:
minimize T
subject to∑
cellsin path
Dproci +
∑
wiresin path
αℓij ≤ T
• one constraint for each path
• variables: T , positions of placeable cells (which determine ℓij)
• a very large number of inequalities
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A more compact representation
• introduce new variable T outi for each cell
• for all cells j, add one inequality for each cell i in the fan-in of j
T outi + αℓij + Dproc
j ≤ T outj (1)
• for all output cellsT out
i ≤ T (2)
• minimize T subject to (??) and (??)
convex optimization problem:
• with ℓ1-norm, get LP
• with ℓ2-norm, get SOCP
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extensions (still convex optimization):
• delay is convex, increasing fct of wire length
• max delay constraints on intermediate cells
• different delay constraints on cells
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Non-convex constraints and generalizations
non-convex constraints
• cells are placed on grid of legal positions
• cells are rectangles that cannot overlap
• reserved regions on chip
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generalizations
• multi-pin nets: share interconnect wires
• combine placement with wire and gate sizing
Problems in VLSI design 47