Transistor sizingce.sharif.edu/courses/86-87/2/ce353/resources/root/... · Transistor sizing nAdjust transistor sizes to achieve desired delay ... nLogical effort is a gate delay

Transistor sizing

Somayyeh KoohiDepartment of Computer Engineering

Sharif University of TechnologyAdapted with modifications from lecture notes prepared by author

Modern VLSI Design: Chap4 2 of 28Sharif University of Technology

Topics

n Transistor sizing:vSpice analysisvLogical effort

Modern VLSI Design: Chap4 3 of 28Sharif University of Technology

Transistor sizing

n Adjust transistor sizes to achieve desired delayvNot all gates need to have the same delayvNot all inputs to a gate need to have the same

delay

Modern VLSI Design: Chap4 4 of 28Sharif University of Technology

Example: adder carry chain

+

+

ai bi

ai

cibi

ci

bi

ai

biai

c i+1

One stage:

Modern VLSI Design: Chap4 5 of 28Sharif University of Technology

Carry chain optimization

n Connect four stagesn Optimize delay through carry chain by

selecting transistor sizes

Modern VLSI Design: Chap4 6 of 28Sharif University of Technology

Case 1n W/L (in terms of µ, and not λ) for all stages:v nmos = 0.75/0.5, pmos = 1.5/0.5

Modern VLSI Design: Chap4 7 of 28Sharif University of Technology

Case 2

n Wider pulldowns for first stage, larger first stage inverter:

Modern VLSI Design: Chap4 8 of 28Sharif University of Technology

Case 3

n Larger transistors in second and third stages:

Modern VLSI Design: Chap4 9 of 28Sharif University of Technology

Inter-stage effects in transistor sizing

n Increasing a gate’s drive also increases the load to the previous stage:

LargerdriveLarger

load

Modern VLSI Design: Chap4 10 of 28Sharif University of Technology

Topics

n Transistor sizing:vSpice analysisvLogical effort

Modern VLSI Design: Chap4 11 of 28Sharif University of Technology

Logical effort

n Logical effort is a gate delay model that takes transistor sizes into account

n Allows us to optimize transistor sizes over combinational networksvNot accurate for circuits with reconvergent fanout

Modern VLSI Design: Chap4 12 of 28Sharif University of Technology

Logical effort gate delay model

n Express delays in process-independent unitn Gate delay is measured in units of minimum-size

inverter delay τ

absddτ

=τ = 3RC

≈ 12 ps in 180 nm process

40 ps in 0.6 µm process

Modern VLSI Design: Chap4 13 of 28Sharif University of Technology

Logical effort gate delay model (Cont’d)

§ Gate delay formula:d = f + p

n Effort delay f is related to gate’s loadn Parasitic delay p depends on gate’s structurev Represents delay of gate driving no loadv Set by internal parasitic capacitance

n Sizes of the transistors in gates does not affect “p”

Modern VLSI Design: Chap4 14 of 28Sharif University of Technology

Effort delay

n Effort delay has two components:v f = gh

n Electrical effort h is determined by gate’s load:v h = Cout/Cin

v Sometimes called fanout

n Logical effort g is determined by gate’s structurev Measures relative ability of gate to deliver currentv g ≡ 1 for inverter

n Logical effort is independent of size, while electrical effort depends on sizes

Modern VLSI Design: Chap4 15 of 28Sharif University of Technology

Delay Plots

d = f + p= gh + p

Electrical Effort:h = Cout / Cin

Nor

mal

ized

Del

ay: d

Inverter2-inputNAND

g =p =d =

g =p =d =

0 1 2 3 4 5

0

1

2

3

4

5

6

Modern VLSI Design: Chap4 16 of 28Sharif University of Technology

Delay Plots

d = f + p= gh + p

n What about NOR2?

Electrical Effort:h = Cout / Cin

Nor

mal

ized

Del

ay: d

Inverter2-inputNAND

g = 1p = 1d = h + 1

g = 4/3p = 2d = (4/3)h + 2

Effort Delay: f

Parasitic Delay: p

0 1 2 3 4 5

0

1

2

3

4

5

6

g = 5/3h = 2

Modern VLSI Design: Chap4 17 of 28Sharif University of Technology

Computing Logical Effort

n Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output currentv Measure from delay vs. fanout plotsv Or estimate by counting transistor widths

A Y A

B

YA

BY

1

2

1 1

2 2

2

2

4

4

Cin = 3g = 3/3

Cin = 4g = 4/3

Cin = 5g = 5/3

Modern VLSI Design: Chap4 18 of 28Sharif University of Technology

Catalog of Gates

22222Tristate / mux(2n+1)/39/37/35/3NOR(n+2)/36/35/34/3NAND

1Invertern4321

Number of inputsGate type

n Logical effort of common gates:

Modern VLSI Design: Chap4 19 of 28Sharif University of Technology

Catalog of Gates

2n8642Tristate / muxn432NORn432NAND

1Invertern4321

Number of inputsGate type

n Parasitic delay of common gates:v In multiples of pinv (≈1)

Modern VLSI Design: Chap4 20 of 28Sharif University of Technology

Logical effort along a path

n Path logical effort G : Logical effort along a chain of gatesv G = Π gi

n Path electrical effort H : Total electrical effort along path depends on ratio of first and last stage capacitances:v H = Cout/Cin

n Path effort F:v F = ∏fi = ∏gi hi

Modern VLSI Design: Chap4 21 of 28Sharif University of Technology

Branching effort

G = 1H = 90 / 5 = 18GH = 18h1 = (15 +15) / 5 = 6h2 = 90 / 15 = 6F = g1g2h1h2 = 36 = 2GHè F ≠ GH

5

15

1590

90

Modern VLSI Design: Chap4 22 of 28Sharif University of Technology

Branching effort (Cont’d)

n Takes into account fanoutn Branching effort at one stage:

b = (Conpath + Coffpath)/ Conpath

n Branching effort along path (Path branching effort B):v B = Π bi

v BH = ∏hi

Modern VLSI Design: Chap4 23 of 28Sharif University of Technology

Path delay

n Path effort F:vF = GBH

n Path delay is sum of delays of gates along the path:vD = Σ gi hi + Σ pi = DF + PvDf : Path effort delayvP : Path parasitic delay

Modern VLSI Design: Chap4 24 of 28Sharif University of Technology

Sizing the transistors

n Delay is smallest when each stage bears same effortv The sum of a set of numbers (Df) whose product (F) is

constant is minimized by choosing all the numbers to be equal

v Optimal buffer chains are exponentially tapered:

v Thus minimum delay of N stage path is

i FD d D P= = +∑

1ˆ Ni if g h F= =

1ND NF P= +

Modern VLSI Design: Chap4 25 of 28Sharif University of Technology

Sizing the transistors (Cont’d)

n Determine W/L of each gate on path by working backward from the last gate:

n Check work by verifying input cap spec is met

i FD d D P= = +∑1ˆ N

i if g h F= =1ND NF P= +

ˆ

ˆ

out

in

i

i

CC

i outin

f gh gg C

Cf

= =

⇒ =

Modern VLSI Design: Chap4 26 of 28Sharif University of Technology

Example: logical effort

n Size transistors in a chain of three two-input NAND gatesvFirst NAND is driven by minimum-size invertervLast NAND is connected to 4X inverter

Modern VLSI Design: Chap4 27 of 28Sharif University of Technology

Example (Cont’d)

n Logical effort G = 4/3 * 4/3 * 4/3n Branching effort = 1n Electrical effort = 4n F = G B H = 9.5n Optimum effort per stage f^ (1/3)= 2.1

Modern VLSI Design: Chap4 28 of 28Sharif University of Technology

Review of Definitions