Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors Martijn Snoeij 1,* , Albert Theuwissen 1,2 , Johan Huijsing 1 and Kofi Makinwa 1 1 Delft University of Technology, The Netherlands 2 Harvest Imaging, Belgium * Now with Texas Instruments, Germany 4 th Fraunhofer IMS Workshop on CMOS Imaging May 6 th , 2008
40
Embed
Power and Area Efficient Column-Parallel ADC Architectures ...harvestimaging.com › pubdocs › 123_duisburg_2008.pdf · Power and Area Efficient Column-Parallel ADC Architectures
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors
Martijn Snoeij1,*, Albert Theuwissen1,2, Johan Huijsing1
and Kofi Makinwa1
1 Delft University of Technology, The Netherlands2 Harvest Imaging, Belgium* Now with Texas Instruments, Germany
4th Fraunhofer IMS Workshop on CMOS ImagingMay 6th, 2008
2
Outline
• Why column-level A/D conversion?
• Application of existing ADC architectures• Development of new ‘custom’ Architectures:
• A key advantage of CMOS imagers is co-integration of analog & digital signal processing ⇒ ‘Camera-on-a-chip’
• On-chip A/D converter essential! Properties:– Complex analog function– Important factor in overall quality– Significant fraction of overall power consumption
• System-level of ADC is of key importance:– Place of ADC within signal processing chain– ADC architecture
4
Chip-Level ADC approach
+ Single ADC: Robust, simple solution
+ ADC separate from imager: ‘standard cell’ can be used
− Single ADC: bottleneck for high readout speeds
5
Column-Level ADC Approach
+ ≈1000 ADCs working in parallel⇒ allows for higher speeds
+ Shorter analog signal path
− Ensuring uniformity between ADCs design problem
− More chip area
6
Pixel-Level ADC Approach
+ ≈1 million ADCs per chip ⇒extremely high frameratespossible
+ Very short analog signal path+ Digital processing within array
possible
− Ensuring uniformity between ADCs design problem
− Very large chip area ⇒impractical for most applications
7
Chip-level ADC (1/chip)
Column-level ADC (≈1k/chip)
Pixel-level ADC (≈1M/chip)
• Power efficiency rather than absolute speed limitations often decisive
• Number of pixels strongly increasing in mainstream imagers ⇒Trend from chip-level towards column-level ADC
Approaches for CMOS Imager A/D Conversion
TotalADC
speed
Complexity /Chip area
8
Architectures for Column ADCs
• What are column ADC requirements:– Small circuit– Uniformity between columns– Good power/speed ratio
• Existing ADC Architectures used in column ADCs:– Cyclic/algorithmic [1-2]– Successive approximation [3-4]– Single-Slope [5-8]
=256clks @ 20MHz=12.8µs frame rate not increased due to digital limitation
Speed increase:• 25% compared to MRSS• 4.1x compared to single-
slope
36
MRMS Architecture Pros & Cons
Advantages:• Further reduction in
conversion time compared to MRSS
• Simple Column circuit• Easy to correct for non-
uniformities
Disadvantages:• Ramp generator more
complex compared to MRSS
• Perceptual impact not fully studied (digital still vsvideo)
• Slight increase in digital overhead
• More details can be found in [11]
37
Summary
• Column-Level ADC provides good trade-off between power-efficiency and complexity for high resolution CMOS image sensors
• Existing ADC architectures have either too complex column circuits or are too slow
• MRSS architecture significantly increases speed and power efficiency of column-level ADC
• Further increase in speed & power efficiency by exploiting photon shot noise with MRMS ADC
38
References
[1] S. Decker, R.D. McGrath, K. Brehmer, and C.G. Sodini, “A 256 x 256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output”, IEEE Journal of Solid-State Circuits, vol 33, no. 12, pp. 2081-2091, Dec. 1996
[2] M. Mase, S. Kawahito, M. Sasaki, Y. Wakamori, and M. Furuta, “A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters”, IEEE Journal of Solid-State circuits, vol. 40, no. 12, pp. 2787-2795, Dec. 2005
[3] Z.Zhou, B. Pain, and E.R. Fossum, “CMOS active pixel sensor with on-chip successive approximation analog-to-digital converter”, IEEE Transactions on Electron Devices, vol. 44, no. 10, pp. 1759-1763, Oct. 1997
[4] B. Mansoorian, H. Yee, S. Huang and E. Fossum, “A 250mW 60 frames/s 1280 x 720 pixel 9b CMOS digital image sensor”, IEEE International Solid-State Circuits Conference, vol. XLII, pp. 312-313, Feb. 1999
[5] W. Yang, O-B. Kwon, J-I. Lee, G-T. Hwang and S-J. Lee, “An integrated 800 x 600 CMOS imaging system”, IEEE International Solid-State Circuits Conference, vol. XLII, pp. 304-305, Feb. 1999
39
References
[6] T. Sugiki et al. , “A 60 mW 10b CMOS image sensor with column-to-column FPN reduction”, IEEE International Solid-State Circuits Conference, vol. XLIII, pp. 108-109, Feb. 2000
[7] K. Findlater et al. , “SXGA pinned photodiode CMOS image sensor in 0.35ìm technology”, IEEE International Solid-State Circuits Conference, vol. XLVI, pp. 218-219, February 2003
[8] Y. Nitta et al. , “High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor”, IEEE International Solid-State Circuits Conference, vol. XLIX, pp. 500-501, Feb. 2006
[9] L. Lindgren, “A new simultaneous multislope ADC for array implementations”, IEEE Trans. On Circuits & Systems II¸ vol. 53, pp. 921-925, September 2006
[10] M.F. Snoeij, P. Donegan, A.J.P. Theuwissen, K.A.A. Makinwa, and J.H. Huijsing , “A CMOS image sensor with a column-level multiple-ramp single-slope ADC”, ISSCC Dig. Tech. Papers¸ pp. 506-507, February 2007
40
References
[11] M.F.Snoeij, A.J.P. Theuwissen, K.A.A. Makinwa, and J.H. Huijsing, “Multiple-Ramp Column-Parallel ADC Architectures for CMOS Images Sensors”, IEEE Journal of Solid-State Circuits, Vol. 42, No. 12, pp. 2968-2977, December 2007
[12] O-B. Kwon et al. , “A Novel Double Slope Analog-to-Digital Converter for a High-Quality 640x480 CMOS Imaging System”, IEEE Int. Conference on VLSI and CAD, pp. 335-338, October 1999
[13] T. Otaka et al., “12-Bit Column-Parallel ADC with Accelerated Ramp”, IEEE Workshop on CCDs and Advanced Image sensors 2005, pp. 173-176, Karuizawa, Japan, June 2005.