Basic Knowledge of Data Converters. Agenda Data Converter Overview ADC/DAC Basics –Sampling Theory –ADC Architectures SAR Delta-Sigma Pipeline Flash –DAC.

Basic Knowledge of Data Converters

Agenda• Data Converter Overview• ADC/DAC Basics

– Sampling Theory– ADC Architectures

• SAR• Delta-Sigma• Pipeline• Flash

– DAC Architectures• R-2R• String

• Data Converter Specifications / Test (how to get them from DATASHEET)– DC Spec.– AC Spec. – ADC/DAC Nomenclature

What is ADC

800000

7FFFFF

0000000TIME

AMPLITUDE

Analog to Digital

What is DAC

800000

7FFFFF

0000000TIME

AMPLITUDE

Digital to Analog

ADC/DAC Basic– Sampling Theory– ADC Architectures

• Delta-Sigma• SAR• Pipeline• Flash

– DAC Architectures• R-2R• String

Basic ADC Theory

• Analog signal is sampled

• The sampled analog signal is compared to one or more reference voltages

• The result of the comparison is converted by digital logic to a binary number.

SHANNON’S information theorem NYQUIST’S Criteria

Shannon:

An analog signal with a Bandwidth of fa must be sampled at a rate

fs>2fa in order to avoid the loss of information.

The Signal Bandwidth may extend from DC to fa (Baseband Sampling)

or from f1 to f2, where fa = f2-f1 (Undersampling, or Super-Nyquist).

Nyquist:

If fs<2fa, then a phenomenon called aliasing will

occur.

Aliasing is used to advantage in undersampling applications

Input SpectrumF(f)

f1 f

Sampled SpectrumG(f)

f1 ffs fs+f1 2fs-f1

Sampled Output

t

g(t)

t1 t2 t3 t4

f(t4)f(t3)f(t2)

f(t1)X =

=*

Sampling Function

Unit Pulsesh(t)

tT

Fourier Transform

NYQUIST'S THEOREM: fs-f1 > f1 fs > 2 f1

Input Waveform

f(t)

tt1 t2 t3 t4

Sampling SpectrumH(f)

ffs = 1/T 2fs

Nyquist region

14-8

Sampling Theory

Oversampling

Why Oversample?• TO MOVE ALIASING FREQUENCY FURTHER FROM THE

DESIRED SIGNAL.• TO RELIEVE ANTIALIASING AND RECONSTRUCTION FILTER

REQUIREMENTS– COST

– COMPLEXITY

– RESPONSE

• TO ALLOW FOR LOWER APPARANT INPUT NOISE BY FILTERING IN THE DIGITAL DOMAIN.

• TO ALLOW FOR LOWER APPARANT INPUT NOISE BY SPREADING THE QUANTIZING NOISE OVER A WIDER BANDWIDTH.

Sampling ADC Quantization Noise

OUTPUT

SIGNAL

RMS QUANTIZATION

NOISE = q/ 12

fs2

fs

Effects of oversampling on Quantization Noise

Analog signal fa sampled @ fs has images

(aliases) at |±Kfs ±fa|, K = 1, 2, 3, ...

0.5fs

0.5fs

fs

fs

1.5fs

1.5fs

2fs

2fs

ZONE 1 ZONE 2 ZONE 3 ZONE 4

fa I I I

I III

I

fa

Effect of oversampling on filter requirement

Analog filter requirement for fo = 10MHz: fS = 30MSPS AND fS

= 60MSPS

fCLOCK = 30MSPS

dB

IMAGE

10 20 30 40 50 60 70 80

fo

ANALOG LPF

10 20 30 40 50 60 70 80

IMAGE

ANALOGLPF

FREQUENCY (MHz)

IMAGEIMAGEIMAGE

IMAGE

fo

fCLOCK = 60MSPS

dB

Undersamplinig

Why Undersample?• The AC bandwidth of the “analog portion” of an ADC is usually wider

than the maximum sample rate.

• Nyquist says that the BANDWIDTH not the FREQUENCY of the

signal must be ½ sampling rate.

• You can process the spectrum at harmonics of the sample rate as well

Undersampling

A

B

C

ZONE 1

ZONE 2

ZONE 3

I

I

0.5fs

0.5fs

0.5fs

fs

fs

fs

1.5fs

1.5fs

1.5fs

2fs

2fs

2fs 2.5fs

2.5fs

2.5fs 3fs

3fs

3fs 3.5fs

3.5fs

3.5fs

Intermediate Frequency (IF) signal at 72.5MHz (±2MHz) is aliased between DC and 5MHz

dc fs

fs= 10.000 MHz 7fs= 70.000 MHz

7fs6fs5fs4fs3fs2fs

sf = 10.000 MSPS

BASEBANDALIAS:

dc TO 5 MHz

SIGNAL:72.5 ± 2 MHz

0 10 20 30 40 50 60 70

Anti-aliasing filter for undersampling

DR

0.5fS fS

fs - f1

Bandpass filter specificationsSTOPBAND ATTENUATION = DR

TRANSITION BAND: f2 TO 2fs - f2

CORNER FREQUENCIES: f1, f2

f1 f2 2fs - f2

1.5fS 2fS0

IMAGESIGNALS

OFINTEREST

IMAGE IMAGE

fc

f1 TO fs - f1

Quantization Error• Analog signals are continuous

• Digital signals have discrete values• A digital word that is converted to an analog signal

will always contain errors• Quantization Error or Noise is dependent on the

number of bits used in the conversion

Quantization

Data Converters’ Architectures• ADCs

– Delta Sigma– SAR– Pipeline– FlashFlash

• DAC– R-2R– String

Customers Talk Architecture???Should you be scared - NOCan you handle it - TRY

Just know the key characteristics and you have just focused in on your device selection

- SAR- Pipeline- Flash- Delta Sigma

A/D Converter

ADC Architectures:

Speed, Resolution, and Latency Analogy

Delta Sigma– 16 to 24 bits of resolution – Typically Slow 10SPS to 105kSPS– Long Latency– If I was a camera I would have my aperture open longer

SAR– 8 to 18 bits of resolution– ~50kSPS to 4MSPS– No latency– If I was a camera I would be have fast shutter speed

Pipeline– 8 to 14 bits of resolution– Up to over 300 MSPS– Some clock cycle latency– I want to be a video camera when I grow up

Flash– 8 to 10 bits of resolution– Up to over 1 GSPS– no latency– I just want to be FLASH

TI Analog to Digital Families

Pipeline

Accuracy (Resolution in bit)

300 M

100 M

10 M

1 M

500 k

100 k

10 k

1 k

0

6 8 10 12 14 16 18 20 24

Delta Sigma

Sp

eed

: S

amp

le R

ate

in

SP

S

SARAdvantagesAdvantages

•No Latency (happens immediately)

•High Resolution and Accuracy (<=18-bits)

•Typically Low Power

•Easy to Use and Multiplex

DisadvantagesDisadvantages

•Typically sample Rates Limited to

Approximately 4 MHz

AdvantagesAdvantages

•Higher Speeds

•Higher Bandwidth


•Lower Resolution

•Pipeline Delay/Data Latency

•More power

Delta Sigma

AdvantagesAdvantages

•High Resolution

•Low cost

•Low Power typically

•High Stability

(averages and filters out noise)


•High Latency

•Low Speed typically

ADC – Successive Approximation Register (SAR) Architecture

An “n” bit SAR converter takes n cycles to complete a conversion.

From most to least significant bit (MSB to LSB) simple compare functions are done and, when a bit is a 1, that amount of voltage is subtracted from the input signal.

SAR’s are workhorse converters… easy to use… simple to understand… but are limited in both resolution and speed.

TI has MANY SAR ADCs.

Ref

VIN

MSB

LSB Dat

a O

ut

fS

+-

S/H

ClockSAR and

Control Logic

D/A Converter

MSB LSB

FS

FS: Full Scale

0

FS2

Successive Approximation ADC

ADC – Pipeline ArchitecturePipeline converters are another high speed architecture. Several lower resolution

converters are put together to result in a fast conversion time. Generally lower power and lower cost than Flash converters, the main disadvantage of a Pipeline converter is that it takes as many clock cycles as there are stages to output the data resulting in latency.

PARALLELDIGITALOUTPUT

ANALOGINPUT

+-

STAGE N

+-

STAGE 1

Sample HoldAmplifier

SAMPLE HOLDAMPLIFIER

Sample HoldAmplifier

DAC

REGISTER

DACADC

REGISTER

ADC

ADC

TI has many Pipelineconverters!

Latency SARs have none….OK, just a little

Aperture delay = 2ηs

Conversion Time = 150ηsAcquisition Time

ADS788112 bits 4MSPS

If it was a 12 bit pipeline with 2 bits/stage, you would need:

Snapshot

150 ηs Conv t Delay = 6.6MSPS X 6 clock cycle delay = 40MSPS

n-7 n-6 n-5 n-4 n-3 n-2 n-1 n

Pipeline A/D ConverterTiming and Data Latency

Analog Input

Clock

InternalS/H

Output Data

Sample Points

S1

S2S3

S4 S5

S6S7

S8

S9

Track

Hold

Track

Hold

Data Latency, 6.5 clock cycles

n+3n n+7n+6n+5n+4n+2n+1

Pipeline A/D ConverterSignal Encoding: SAR vs. Pipeline

• SAR: Serial Encoding

Sample #1

• Pipeline: Parallel Encoding

Sample #3

Sample #2

Sample #1

MSB

MSB

MSB

LSB

LSB

LSB

B2

B2

B2

B3

B3

B3

B4

B4

B4

B5

B5

B5

B6

B6

B6

B7

B7

B7

Conversion Time

Conversion Time

MSB LSBB2 B3 B4 B5 B6 B7

And Now for something completely differentDelta Sigma’s

Delta-Sigma Overview• What is a delta-sigma ADC?

– A 1-bit converter that uses oversampling (can be multi-bit)– “Delta” = comparison with 1-bit DAC– “Sigma” = integration of the Delta measurement

• What is the advantage of delta-sigma?– Essentially digital parts which result in low cost– High resolution

• What are the disadvantages?– Limited frequency response– Most effective with continuous inputs– Latency

3

Converters – Functional Block Diagram

AnalogInput

1-bitwide

n-bitswide Digital

OutputDigitalFilter

AnalogModulator

PGA

Advantages:• Minimum analog components• Integrates easily with digital logic• Oversampling reduces inband

noise

Disadvantages:• Speed limited to upper audio

range

Delta-Sigma A/D Converters

Delta-SigmaModulator

AnalogInput

DigitalFilter

DecimatorDigitalOutput

Digital Decimating Filter(usually implemented as a single unit)

Delta-Sigma A/D Signal Path


AnalogInput

DigitalFilter



You are here


MAGNITUDE

FREQUENCYTIME

AMPLITUDE

TIME DOMAIN FREQUENCY DOMAIN



AnalogInput

DigitalFilter





0

1

Believe it or not, the sinewave is in there!

(drawing is approximate)

QUANTIZATIONNOISE

Fs

SIGNAL



QUANTIZATIONNOISE

Fs

SIGNAL

800000 (-FS)

7FFFFF (+FS)



AnalogInput

DigitalFilter





800000

7FFFFF

0000000

QUANTIZATIONNOISE

Fs

SIGNAL



AnalogInput

DigitalFilter





800000

7FFFFF

0000000

QUANTIZATIONNOISE

ORIGINAL Fs

SIGNAL

Fd

ALIAS


SIGNAL FROM MODULATOR

OUTPUT OF DECIMATING FILTER

800000

7FFFFF

0000000

800000 (-FS)

7FFFFF (+FS)

DECIMATING FILTER

Oversampling, digital filter, NOISE SHAPING, AND DECIMATION

Kfs

fs

2

fs

Kfs

2

KfsKfs

2

fs

2

fs

2

DIGITAL FILTER

REMOVED NOISE

REMOVED NOISE

QUANTIZATIONNOISE = q / 12 q = 1 LSBADC

ADCDIGITALFILTER

MOD

DIGITALFILTER

fs

Kfs

Kfs

DEC

fs

NyquistOperation

Oversampling+ Digital Filter+ Decimation

Oversampling+ Noise Shaping+ Digital Filter+ Decimation

A

B

C

DEC

fs

The Delta-Sigma Modulator

To DigitalFilter

Signal input, X1

X2

X3X4

X5

DifferenceAmp

IntegratorComparator(1-bit ADC)

1-bit DAC

+

-+

-

VMax

Delta Sigma

4

Signal input, X1 X2X3 X4

X5

DifferenceAmp

IntegratorComparator(1-bit ADC)

1-bit DAC

To DigitalFilter

+

-+

-

VMax

X1

X2

X3

X5

Vmax

0V

+Vmax

-Vmax

La

tch

X4

+Vmax

-Vmax

1

0

Vmax

0V

Delta-Sigma Modulator

Averaging Filters

0V

Full-scaleDelta-Sigma Modulator

DC input levels

1-bit data

1-bit data streams1/2 full-scale input 1/4 full-scale input 3/4 full-scale input

1 1 10 Average 0 Average 1 Average1 = 0.5 0 = 0.25 1 = 0.750 0 01 1 10 0 11 0 10 0 0

The Frequency Domain

FrequencyFS / 2 FS

Signal amplitude

Quantization Noise

SNR = 6.02N + 1.76dB ; (for an N-bit ADCSine wave input)

Average noise floor (flat)

Po

we

r

Oversampling by K Times

Frequencyk FS / 2 k FS

Average noise floor

Oversampling by K times

Po

we

r

Same total noise, but spread over more frequencies

SNR = 6.02N + 1.76dB ; (for an N-bit ADCSine wave input)

The Digital Filter

Frequency

k FS / 2 k FS

Noise removed by filter

Oversampling by K times

Ideal digital filter response

BW

Po

we

r

SNR = 6.02N + 1.76dB + 10 log(Fs/2*BW)

Noise-Shaped Spectrum

Frequency

k FS / 2 k FS

Signal Amplitude

The integrator serves as ahighpass filter to the noise.

The result is noise shaping

Po

we

r

SNR = 6.02N + 1.76dB

Vin(t) Integrator

D/A

CLK

Dout(t)

1st order Modulator

Filtering the Shaped Noise

Signal amplitude

HF noise removedby the digital filter

Digital filter response

Frequency

k FS / 2 k FS

Po

we

r

The 2nd Order Delta-Sigma Modulator

-

+

1-bit DAC

∑

1-BIT ADCINTEGRATOR

1-BIT OUTPUT

-

+

∑

INTEGRATOR

N2 f( ) 4 erms 2 T sin2 f T

2

2

SPECTRAL QUANTIZATION NOISE DENSITY

yi

xi 1 e

i2 e

i 1 ei 2 MODULATOR OUTPUT


0 100 200 300 400 500

1st-order2nd-order3rd-order4th-order

Modulator noise densities

Hz


0 1 2 3 4 5 6 7

1st-order2nd-order3rd-order4th-order

Modulator noise densities

Hz

Sampling speed vs. ENOB

QUANTIZATIONNOISE

Fs

SIGNAL

Fd

ADC Topology Summary

Slow, moderate cost.Up to 24-bit

Up to 16-18 bits

< 100ksps

< 10MSPS

Delta-Sigma

Up to 16-bit< 200MspsPipeline

Fast, expensive, large power requirements.

Up to 10-bit< 500MspsFlash

Simple operation, low cost, low power.

Up to 18-bit< 5MspsSAR

CommentsResolutionF ConversionADC

Topology

Fast, expensive, large power requirements.

6

D/A Converter– R-2R– String– Current Steering

TI DAC Technologies

Settling Time- s

20

16

12

8

Current

Steering

Resistor String

& R-2R

Co

nve

rter

Res

olu

tio

n

6810 4 2 1 .05 .0011001000

Current Technology

High Speed Video and CommunicationUpdate rate (MSPS)Typically 1 Output but a few 2 OutputCurrent out

IndustrialSettling Time (µs)Number of Out put DACsResistor String – InexpensiveR-2R – More accurate -Trimmed at final test Typically Voltage outMDAC’s (dig control gain/atten, Waveform gen.)

Instrumentation and MeasurementTypically for Calibration

Setling time

1/UpdateRate

R-2R Architecture

+

-

2R 2R 2R 2R 2R 2R 2R 2R 2R

R R R R R R R

R

LSB MSB

VR E F

( VOUT )

ANALOGOUTPUT

+ small. Only 2*N resistors required

- tight resistor matching required

- not inherently monotonic

Resistor String DAC Architecture

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0 V

7/8 VR E F

V R EF

+

-

LSB MSB1 10

VOU T

R

R

R

R

R

R

R

R

6/8 VR E F

5/8 VR E F

4/8 VR E F

3/8 VR E F

2/8 VR E F

1/8 V R E F

VFB

= VREF (bi/2i)

Typical Block Diagrams of a Resistor String DAC

V R EF

D AC R EGIST ER R ESIST OR ST R IN G

R EF (+)

R EF (- )

G ND

+

-VOU T

VFB

C ontro l andInter face

x2 VOU TD AC Latch

Buffer

VR EF

Data

C lock / W E

C S

(a)

(b)

IOUT

IOUT

2N-1 Current Sources

Switches determined by digital input

Current Steering DACs

III

Precision DAC Product Strategy

• Expensive• High Accuracy

• Low Cost• High Accuracy• Great AC Specifications• Small Packages• High Channel Counts• Single and Dual Supply

Output Ranges

More BACK

• Low Cost• Limited Accuracy

0 1 10 16 32 64

15

10

5

0

INL (LSB)

Set

tling

Tim

e (µ

s)

HPA07

Current Steering typically settles to 0.1% Precision DACs (R-2R and String) to .003%

DAC Architecture Positioning

* INL is at the 16-bit level

Higher Power Consumption

BACKMore

Data Converter Specifications

Evaluating the ADC (Datasheet)

Key Performance Characteristics

• DC– Offset error– Gain error– Differential linearity– Integral linearity

• AC– SNR– THD– SFDR

• Others

N = Resolution of ADC1 LSB =VFULLSCALE(nom.)

2N

N = 8 10 12 14 16 20

1 LSB 39.06 9.77 2.44 610 153 9.53± 5 V input range mV mV mV V V V

1 LSB 19.53 4.88 1.22 305 76.3 4.77 + 5 V input range mV mV mV V V V

1 LSB 11.72 2.93 732 183 45.8 2.86+ 3 V input range mV mV V V V V

How Large is an LSB ?

Resolution vs. Accuracy:

4

Good AccuracyPoor Resolution

Poor AccuracyPoor Resolution

Poor AccuracyGood Resolution

Good AccuracyGood Resolution

AC SpecsSNR (Signal-to-Noise Ratio) –

• RMS value representing the ratio of the amplitude of the desired signal to noise power below one half the sampling frequency.

• Measure of the strength of a signal to background noise. • Contributes to the overall dynamic performance of the

device at higher frequencies and affects the linearity at those frequencies.

• In the audio world, a low signal-to-noise ratio means the device has lots of hiss and static, while a high rating means clear-sounding audio.

THD (Total Harmonic Distortion) – • The ratio of the sum of the powers of all harmonic

frequencies above the fundamental frequency to the power of the fundamental frequency.

• THD is usually expressed in dB.

ENOB (Effective Number Of Bits) - • The number of bits achieved in a real system. • Is another way of specifying the SNR. • ENOB = (SNR-1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this ENOB number of bits.

SFDR (Spurious Free Dynamic Range) - • The headroom available in an FFT plot.• It is the distance in dB between the fundamental input and

the worse spur.

Fundamental Signal

SFDR

First Harmonic

Second Harmonic

Average Noise Floor

DC errors

Gain Error – • The gain error is the difference between the ideal gain between zero and full scale on the transfer function and the actual gain after the offset error

has been corrected to zero. • This error represents a difference in the slope of the actual and ideal transfer functions and as such corresponds to the same percentage

error in each step. • This error can also usually be adjusted to zero by trimming.

000

001

010

011

100

101

110

111

Offset Error

Ideal Transfer Function

Actual Transfer Function

Ideal Full Scale Range

Actual Full Scale Range

Offset Error – • The offset error is the difference between the nominal and actual offset points. • It is the difference in voltage between the first ideal code transition and the actual code transition of the ADC. • This error affects all codes by the same amount and can usually be compensated for by a trimming process. If trimming is not possible, this error is

referred to as the zero-scale error.

Analog Input Voltage

Dig

ital

Out

put

code

DC Specs

DNL (Differential Nonlinearity Error) – (or simply differential linearity) • The differential nonlinearity error is the difference between an actual step width (for an ADC) or step height (for a DAC) and the ideal

value of 1 LSB (Least Significant Bit). • If the DNL exceeds 1 LSB, the magnitude of the output gets smaller for an increase in the magnitude of the input. • In an ADC there is also a possibility that there can be missing codes (if DNL < -1LSB) i.e. one or more of the possible 2n binary codes are never

output.

INL (Integral Nonlinearity Error) - (or simply linearity error)• The deviation of the values on the actual transfer function from the ideal transfer function once the gain and offset errors have been

nullified.• The summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the INL at that step. • The unit for INL is LSB.

000

001

010

011

100

101

110

111

Ideal Transfer Function

Actual Transfer Function


Dig

ital

Out

put

code

< 1LSB DNL

> 1LSB DNL

INL < 0

Major DNL Errors

111

110

101

100

011

010

001

0000 1 2 3 4 5 6 7

Input Voltage

ADC Missing Code

LOST???

Different Datasheets list specs in different terminologies– INL in LSB, mV, %, PPM

– Power in mW, V, I

– Gain error/drift in %FSR, μV

The Relevancy…

LSB mV % PPM

LSB * LSBX(2)[1].VrefX100

2N

LSB X 100

2N

LSB X 106

2N

mV mV X 2N .

(2)[1].Vref 100* mV .

(2)[1] Vref

mV X 104

(2)[1] .Vref

% % X 2N

100

% X (2)[1] .Vref * % X 104

PPM PPM X 2N

104

PPM X (2)[1] .Vref

100

PPM

104 *[1] The factor 2 in brackets is to be used for a bipolar device.

Cheat Book

Power (W) = Vin (V) X Ioper (A)

111

110

101

100

011

010

001

0000 1 2 3 4 5 6 7

Out

put

Cod

e

Input Voltage

Ideal transfer characteristic

Actual transfer characteristic

ADC Offset Errors

10

111

110

101

100

011

010

001

0000 1 2 3 4 5 6 7

Out

put

Cod

e

Input Voltage

ADC Gain Errors

11

111

110

101

100

011

010

001

0000 1 2 3 4 5 6 7

Out

put

Cod

e

Input Voltage

ADC INL Errors

13

111

110

101

100

011

010

001

0000 1 2 3 4 5 6 7

Out

put

Cod

e

Input Voltage

ADC DNL Errors

12

111

110

101

100

011

010

001

0000 1 2 3 4 5 6 7

Out

put

Cod

e

Input Voltage

DNL Major Errors

12

111110101100011010001000

0

1

2

3

4

5

6

7

Out

put

Vol

tage

Input Code

ADC Missing CodeDAC Non-monotonic

Dynamic SpecificationsA

mp

litu

de

(dB

)

0-10-20-30-40-50-60-70-80-90

-100-110-120-130

0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k Frequency - Hz

FundamentalF

H2 H3 H4 H5 H6 H7 H8 H9

Harmonics

14-30

Spurious Free Dynamic Range (SFDR)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-1300 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k

Frequency / Hz

Fundamental F

SFDR

Am

plit

ud

e (d

B)

14-32

Am

pli

tud

e (d

B)

0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k

Frequency / Hz

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

f2 - f1 2f1 - f2

f1 f2

2f2 - f1 f1 + f2

Intermodulation Distortion, IMD

14-33

Measuring Noise

• RMS noise– Usually calculated from standard

deviation of a series of samples– Used to calculate ENOB– Does not depend on noise type

• Peak-to-peak noise– Gives “display resolution”– Estimates typically assume that the noise

is Gaussian

Measuring Noise

Calculating RMS noise

2

2

0

2

2

log ENOB

)(

M

N

xxN

ii

Variance of a set of N samples:

Standard deviation:Effective number of bits (if samples are ADC codes):

Measuring Noise

Peak-to-peak noise

( 3.3 , 3.3 )X XX X

For Gaussian noise, > 99.9% of samples occur in the interval:

Then our rule of thumb is:

Peak-to-peak noise = 6.6 * RMS noise

Signal to Noise Ratio (SNR)

SNR =VSIN

VN

N is number of bits of resolution

Each extra bit provides approximately6 dB improvement in the SNR !

Effective Number Of Bits (ENOB):

SNR(dB) = 6.02 N + 1.76

Quantization Noise

+Q/2

-Q/2Q

ENOB =(SNR + D)(dB) - 1.76

6.02

111

110

101

100

011

010

001

000FS0.5 FS


Dig

ital

Ou

tpu

t C

od

e

Q

14-29

Definition of "NOISE-FREE" code resolution

Effective resolution

= log2

Full scale rangeRMS noise bits

Noise-freeCode resolution = log2

Full scale rangeP-P noise

P-Pnoise = 6.6 × RMS noise(most commonly used ratio)

= effective resolution – 2.72 bits

Typical output RMS NOISE in uVand effective resolution in bits

First Notch of Filterand O/P Data Rate

-3 dBFrequency G = 1 G = 4 G = 16 G = 128

Output Noise:

10 Hz 2.62 Hz 1.7 0.5 0.36 0.36

60 Hz 15.72 Hz 8.5 2.0 0.6 0.45

250 Hz 65.5 Hz 130 25 7.5 1.7

1 kHz 262 Hz 3.1 x 103 0.7 x 103 180 40

Effective Resolution:

10 Hz 2.62 Hz 21.5 21.5 19.5 16.5

60 Hz 15.72 Hz 19.5 19 19 16.5

250 Hz 65.5 Hz 15.5 15 15 14.5

1 kHz 262 Hz 10.5 11 11 10

Device (Semiconductor, Resistor) Noise Dominates at the Lower

Frequencies (< 60 Hz notch)

Quantization Noise Dominates at the Higher Frequencies

The Aperture Error isless than 1 LSB, if:

In a 12-bit system with a maximum signal frequency of 20 MHz, the Aperture-Jitter has to be less than 3.8 ps !

Aperture-Jitter (Sampling Uncertainty)

t

A

V

VP

-VP

TA

tA

vV+ v

1 10 100 1000Maximum Signal Frequency (MHz)

* Equivalent converter SNR

SN

R(d

B)

130

120

110

100

90

80

70

60

50

40

30

*14 Bit

*12 Bit

*16 Bit*16 Bit

0.1 ps

0.3 ps

1 ps

3 ps

10 ps

Jitter Limits

– What is meant by 4 SE or 4 Diff?

– What is meant by 3x2 Diff?

Number of Input Channels

Multiplexer

ADC

Multiplexer

Multiplexer

ADC

ADC

Number of Input Channels

Single Ended (SE) vs Differential (Diff)

• SE: – Referenced to ground

– Grounds may not be the same across causing a noisier environment

• Diff:– Full-scale Range

– Wider code steps

– More accurate

Ain

Ain+

Ain-

ADC Interface SolutionsPrinciple Configuration Choices

Single-Ended Input Differential Input

ADCADC

Input+ fs

Vcm

- fs

Vcm

IN

IN

IN

IN

+ fs/2 Vcm-fs/2

+ fs/2 Vcm-fs/2

Requires full input swing from +fs to –fs2x the swing compared to differentialInput signal at IN typically requires a common-mode voltage for biasInput IN\ also requires a Vcm for correct dc-bias

Combined Differential inputs result in full-scale input of +fs to –fsEach input only requires 0.5x the swing compared to single-endedBoth inputs require a Vcm for correct dc-bias

SPI

MOSI

SCLK

MISO

DCLK

ADS8344

D IN

BUSY

D OUT

CS SS

GPI

CH0

CH7

Typical SPI Interface

43

I2C Interface — DSPs

C55XXI2C

C55XXI2C

SDA

SCL

ADS7828

V DD

2k2k

ADS7828

SDA

SCL

CH0CH1

CH7

CH0CH1

CH7

48

Digital SignalProcessor

CLK

R/W

GPO

GPI

D[15..0]

CLK

ADS8322

D[15..0]

CONVST

BUSY

CS GPO

RD decoderA[19:0]

Digital SignalProcessor

CLK

R/W

GPO

INT

CLK

ADS8322

CONVST

BUSY

CS GPO

RD logicA[19:0]

D[15..0] D[15..0]

logic

Parallel—Digital Signal Processor

Figure 1 Figure 2

46

Pseudo-Differential Mode ADC’s

ADC DAC

AIN(+)

AIN(-)

+/- 200mV Maximum

Pseudo-Differential Mode ADC’s

AIN(-)

AIN(+)

DAC OUTPUT

Digital Change Delay Time t

Glitch

Settling Time, ts

Final Value

ErrorBand

An

alo

g O

utp

ut

(V)

Settling time of a DAC

Monotonicity

A DAC is monotonic if its output either increases or remains constant as the digital input increases, with the result that the output will always be a single-valued function of the input.

Glitch Improvement

• Main Cause of Glitch– Charge in the switch causes

node voltage to change temporarily

– More number of switches toggling when code changes – more glitch!!

• TSMC products uses Row-Column decoding (see next slide) – 30~40 switches toggling at any code change

• HPA07 products uses single decoder – maximum of two switches toggling at any time

a

+

-V FB

V IN

VOUT

R

fb

R t

Charge Q

gets split

ADC Nomenclature

• TI ADCs- TLC/TLVxxxx

0 or Blank 8-Bit1 10-Bit2 12-Bit3 14-Bit4 16-Bit7 4½ Digit

TLC: 5VTLV: 3V

• HS ADCs Not IncludedADS51xxADS52xxADS54xxADS55xxADS8xxTHS14xxTHS12xxTHS10xx

• BB ADCs & Future- ADS1xxx Delta-Sigma ADCs (except ADS1286 SAR)

ADS1xxx: 12-BitADS11xx: 16-BitADS121x: 24-Bit, IntegratedADS122x: 24-Bit, Low PowerADS123x: 24-Bit WeightADS125x: 24-Bit ProgrammableADS127x: 24-Bit Fast AC/DCADS16xx: 16-/18-Bit Wide

Bandwidth

- ADS78xx/ADS8xxx SAR/Nyquist ADCsADS78xx: 8-/10-/12-/14-/16-Bit

<1MSPSADS83xx: 16-/18-Bit <1MSPSADS84xx: 16-/18-Bit >1MSPSADS85xx: 12-/16-Bit +/-10V

- THS10xxx/12xx, TLV12xx/15xx High-speed (<10 MSPS)

All Future DAP ADCs Will Have ADS Prefix!

DAC Nomenclature

• TI 8-/10-/12-Bit DACs- TLC/TLV56xx

TLC: 5 V

TLV: 3 V

• High Speed CMOS DACs

(Update Rate > 40MSPS)DAC56xx

DAC9xx

DAC29xx

THS56xx

• Delta Sigma DACs DAC1xxx: 14/16-Bit

• Burr-Brown and Newer TI DACs- DACx5xx String DACs (0 to +5 V)

DAC55xx: 8-Bit, I2C, Unipolar

DAC65xx: 10-Bit, I2C, Unipolar

DAC751x: 12-Bit, SPI, Unipolar

DAC754x: 12-Bit, Parallel, Bipolar

DAC755x: Enhanced 12-Bit, SPI, Unipolar

DAC757x: 12-bit, I2C, Unipolar DAC85xx 16-bit, Serial or Parallel, Unipolar or Bipolar

- DAC76xx R-2R DACs (0 to +2.5 V & +/-2.5 V)

DAC76xx: 12-/16-Bit, SPI or Parallel, Bipolar

- DAC77xx R-2R High-voltage DACs (0 to +10 V & +/-10 V)

DAC77xx: 12-/16-Bit, SPI or Parallel, Bipolar

- DACx8xx R-2R Multiplying DACs. 2nd Source to ADI/LTC DAC78xx: 12-bit, SPI or Parallel

DAC880x: 14-Bit, SPI or Parallel

DAC881x: 16-Bit, SPI

DAC882x: 16-Bit, Parallel

- DAC883x: R2R DAC 16-Bit, SPI, Low Power, Best INL/DNL

Thanks!Questions?

Basic Knowledge of Data Converters. Agenda Data Converter Overview ADC/DAC Basics –Sampling Theory –ADC Architectures SAR Delta-Sigma Pipeline Flash –DAC.

Documents

f s f

f s slide

rate f s

bandwidth of f

analog slide

dcf s f s

analog signal f

kf s f