Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements Muhammad Bashir and Linda Milor Georgia Institute of Technology ĸHISTORICALLY, THE MAJOR CAUSE of interconnect wearout has been electromigration. Recently, be- cause of the introduction of new materials (copper, low-k dielectrics), the increase in the number of inter- connect layers with smaller geometries and higher current densities, and the concomitant increase in on-chip temperatures, low-k dielectric breakdown and stress migration have emerged as new sources of interconnect wearout. This article focuses on mod- eling one of these new wearout mechanisms: low-k dielectric breakdown. In the past, the lifetime of the dielectric between interconnect lines has not been a concern, because of the dielectric’s thickness. However, in recent years copper and low-k interconnect systems have become vulnerable to breakdown because of the lower breakdown field strengths of porous low-k materials, the susceptibility of low-k materials to mechanical damage by chemical mechanical pol- ishing (CMP), and the high susceptibility of low-k materials to copper drift. These problems are com- pounded because the supply voltage is not scaled as aggressively as feature size, which results in exponentially escalating electric fields among inter- connects in each technology generation. Porosity degrades the electrical and structural properties of copper and low-k systems further, because of, for example, the absorption of chemi- cals through pores that have an open connection to the surface. Back-end dielectrics differ from thin gate oxides in several ways. First, unlike the gate oxide, the back-end dielectric undergoes many process steps that can potentially damage the interfaces, which can become trap sites and assist in conduc- tion. Second, the quality of the back-end dielectric, which is deposited rather than thermally grown, is far poorer, resulting in higher defect densities. Third, back-end geometries in chips have a wide variety of geometries that might impact chip lifetime. The ap- propriate features to extract from a chip and the fail- ure rates to measure from test structures are not known. As a result, time-dependent dielectric break- down (TDDB) of damascene structures must be assessed as a system consisting of a dielectric, diffu- sion barrier, cap layer (SiC, for example), and copper interconnect. Figure 1a shows an example of this system. In this article, we explore how interconnect geom- etry impacts failure rates and describe our failure-rate models for determining the time-to-fail at small per- centiles (the tails of the distribution) while account- ing for the observed curvature in Weibull plots. We use the data we obtained from back-end dielectric breakdown lifetime measurements directly to deter- mine the impact of line width variation. We also dis- cuss how we use this information to determine equivalent lifetime requirements that consider both the impact of die-to-die line width variation and the traditional failure rate distribution, modeled by Wei- bull statistics. Design for Reliability at 32 nm and Beyond Editor’s note: Low-k dielectric breakdown and stress migration have emerged as new sources of wearout for on-chip interconnect. This article analyzes statistical data from a 45-nm test chip and constructs a methodology to determine the lifetime of low-k materials under process variations. Yu Cao, Arizona State University 0740-7475/09/$26.00 c 2009 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers 18
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Modeling Low-k DielectricBreakdown to DetermineLifetime RequirementsMuhammad Bashir and Linda Milor
Georgia Institute of Technology
�HISTORICALLY, THE MAJOR CAUSE of interconnect
wearout has been electromigration. Recently, be-
cause of the introduction of new materials (copper,
low-k dielectrics), the increase in the number of inter-
connect layers with smaller geometries and higher
current densities, and the concomitant increase in
on-chip temperatures, low-k dielectric breakdown
and stress migration have emerged as new sources
of interconnect wearout. This article focuses on mod-
eling one of these new wearout mechanisms: low-k
dielectric breakdown.
In the past, the lifetime of the dielectric between
interconnect lines has not been a concern, because
of the dielectric’s thickness. However, in recent
years copper and low-k interconnect systems have
become vulnerable to breakdown because of the
lower breakdown field strengths of porous low-k
materials, the susceptibility of low-k materials to
mechanical damage by chemical mechanical pol-
ishing (CMP), and the high susceptibility of low-k
materials to copper drift. These problems are com-
pounded because the supply voltage is not scaled
as aggressively as feature size, which results in
exponentially escalating electric fields among inter-
connects in each technology generation. Porosity
degrades the electrical and structural properties
of copper and low-k systems further, because of,
for example, the absorption of chemi-
cals through pores that have an open
connection to the surface.
Back-end dielectrics differ from thin
gate oxides in several ways. First, unlike
the gate oxide, the back-end dielectric
undergoes many process steps that
can potentially damage the interfaces,
which can become trap sites and assist in conduc-
tion. Second, the quality of the back-end dielectric,
which is deposited rather than thermally grown, is
far poorer, resulting in higher defect densities. Third,
back-end geometries in chips have a wide variety of
geometries that might impact chip lifetime. The ap-
propriate features to extract from a chip and the fail-
ure rates to measure from test structures are not
known. As a result, time-dependent dielectric break-
down (TDDB) of damascene structures must be
assessed as a system consisting of a dielectric, diffu-
sion barrier, cap layer (SiC, for example), and copper
interconnect. Figure 1a shows an example of this
system.
In this article, we explore how interconnect geom-
etry impacts failure rates and describe our failure-rate
models for determining the time-to-fail at small per-
centiles (the tails of the distribution) while account-
ing for the observed curvature in Weibull plots. We
use the data we obtained from back-end dielectric
breakdown lifetime measurements directly to deter-
mine the impact of line width variation. We also dis-
cuss how we use this information to determine
equivalent lifetime requirements that consider both
the impact of die-to-die line width variation and the
traditional failure rate distribution, modeled by Wei-
bull statistics.
Design for Reliability at 32 nm and Beyond
Editor’s note:
Low-k dielectric breakdown and stress migration have emerged as new
sources of wearout for on-chip interconnect. This article analyzes statistical
data from a 45-nm test chip and constructs a methodology to determine the
lifetime of low-k materials under process variations.
��Yu Cao, Arizona State University
0740-7475/09/$26.00 �c 2009 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers18
Back-end dielectric reliabilityBack-end dielectric reliability is measured with
comb test structures, as illustrated in Figure 1b. The
comb structures create a lateral stress across the dielec-
tric between the comb fingers, which are separated by
the minimum-space design rule. A voltage difference is
applied to the comb, creating a lateral electric field
through the intralayer dielectric. The current between
the comb fingers is monitored, and breakdown is
observed when the current exceeds a fixed threshold.
In collecting data for a sample of comb structures,
we order the data from shortest to longest breakdown
time. We assign each time point a probability point, P,
by partitioning the probability scale equally. Figure 2
shows an example.
The data is fit by a distribution, either the Weibull
or the lognormal distribution, in order to enable
extrapolations to lifetimes at low percentiles. Let’s
consider the Weibull distribution, as an example.
When constructing a model by fitting a Weibull distri-
bution to a dataset, two parameters are extracted: the
characteristic lifetime (62.5% probability point) Z and
the shape parameter b. The intercept of the x-axis is Z,
and the slope of the curve is b. The resulting data is
then scaled to use conditions and to the vulnerable
area corresponding to the chip.
When considering layout geometries, we note that
field enhancement occurs at the tips of the comb
structures. Prior work has indicated that failure sites
correspond with locations where there is field en-
hancement.2,3 To address this concern, we have
designed a set of test structures that can separate
the impact of field enhancement at the comb tips.
Analysis of data from these test structures has
required developing a methodology to determine fail-
ure rates for structures containing multiple feature
geometries��that is, parallel lines and tips.
The result of data analysis is the construction of an
accurate model to determine failure rates at low per-
centiles. As Figure 2 shows, the data points do not fall
on a straight line, as expected for Weibull statistics.
Chen et al. noted that line width variation can be
as large as �30%.4 This variation distorts the Weibull
curves used to determine a structure’s lifetime. As a
result, direct extraction of parameters Z and bwould be inaccurate.
Die-to-die line width variation can be eliminated
during Weibull parameter extraction through calibra-
tion of lifetime measurements based on capacitance
measurements, which can be used to compute the
mean distance between the lines of the comb struc-
ture.4 However, because of the structure’s complexity,
capacitance is also affected by variation in the low-k
dielectric constant as a function of the stack’s compo-
sition, and variation in the dielectric constant is con-
sequently confounded with variation in line space.
Hence, capacitance measurements overestimate
line width variation.
Impact of field enhancementTo determine the impact of field enhancement, we
conducted several experiments. Here, we discuss
(a) (b)
BarrierTEOS
SiC
Cu Cu
SiONPSG
SiC
Dielectric Dielectric
Figure 1. Cross-section of an example copper and low-k
interconnect system, including the barrier layer and cap
layer (a), and comb test structure used to measure back-end
dielectric breakdown (b).
–6
–5
–4
–3
–2
–1
0
1
2
3
4 6 8 10 12
ln(time) [a.u.]
ln(–
ln(1
–P))
1X 3X 4.5X 9X
Figure 2. Example Weibull plot of ln(2ln(1 2 P)) vs.
ln(time-to-failure(i)) for comb test structures with four
areas: 13, 33, 4.53, and 93. (Source: Bashir and Milor.1)
19November/December 2009
previous data acquired from some of our earlier
work, which indicated the potential impact of field
enhancement at the tips of combs on low-k dielectric
lifetimes.
Role of field enhancement in breakdown
It is generally assumed that the vulnerable area in
the comb test structure is solely a function of the area
and distance between the comb fingers. However, the
electric field between the comb fingers is nonuni-
form, and there is significant field enhancement at
the comb tips.
To analyze back-end geometries, a set of circuits
were synthesized using standard placement and rout-
ing tools from which we extracted the most frequent
patterns in the back-end geometries. Besides parallel
lines, several patterns were frequently found,2 includ-
ing terminating lines and lines with bends.
For each of these structures, a 3D finite element
was constructed to determine the electric field distri-
bution. The field was found to be highly nonuniform,
with peak fields from some geometries exceeding
that of the parallel line structure by a factor of 2
to 3.2 High fields could also be found at the top
(cap layer) and bottom interfaces for all structures
because of the sharp edges.2 These high fields at
the top, cap layer interface are especially problematic
because this interface is formed by CMP. This is a low-
quality interface, which contains many dangling
bonds, facilitating copper ion drift or the formation
of a percolation path.
Note that the test structure in Figure 1b has two
types of geometry: parallel lines with a minimum dis-
tance between them, and tips. Field enhancement
can potentially occur at the tips. Our experimental
results for 0.18-micron technology, involving stressing
a set of industrial comb structures made with copper
and low-k materials, indicated the potential role of
field enhancement, because even though the test
structures have long parallel lines with minimum
space, most failure sites coincided with peaks in elec-
tric field at the tips in the structure. Examples, avail-
able elsewhere,2 are similar to results achieved by
Chen et al.,3 in which failure sites also coincided
with electric field enhancement.
Test structures and data collection
In the work we report on here, we designed test
structures to isolate the failure rates of parallel lines
and tips. To isolate the rates, pairs of test structures
are needed to extract each target feature. For extrac-
tion of area and tips, one of the test structure pairs
holds area constant and varies tips, whereas another
pair holds the number of tips constant and varies
area. The smallest test structure with unit area and
tips is labeled as (1�, 1�).
Other test structures have area and tips that are a
multiple of the unit test structure. A test structure
with M times more area and N times more tips is la-
beled as (M�, N�). We used a matrix of test struc-
tures that include the following area and tip pairs: